Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.68			81.68

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_dm	81.68			81.68

---

Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.68			81.68

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.68			81.68

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	82	50	60.98
Total Bits	906	740	81.68
Total Bits 0->1	453	370	81.68
Total Bits 1->0	453	370	81.68

Ports	82	50	60.98
Port Bits	906	740	81.68
Port Bits 0->1	453	370	81.68
Port Bits 1->0	453	370	81.68

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
ndmreset_req_o	Yes	Yes	T28,T55,T29	Yes	T28,T55,T29	OUTPUT
dmactive_o	Yes	Yes	T6,T26,T37	Yes	T28,T53,T55	OUTPUT
debug_req_o	Yes	Yes	T55,T128,T129	Yes	T55,T128,T129	OUTPUT
unavailable_i	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.d_ready	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[3:0]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_user.data_intg[4]	No	No		No		INPUT
regs_tl_d_i.a_user.data_intg[5]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_user.data_intg[6]	No	No		No		INPUT
regs_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
regs_tl_d_i.a_user.cmd_intg[4:2]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_user.cmd_intg[5]	No	No		No		INPUT
regs_tl_d_i.a_user.cmd_intg[6]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_d_i.a_user.instr_type[3]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_data[1:0]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_data[3:2]	No	No		No		INPUT
regs_tl_d_i.a_data[5:4]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_data[7:6]	No	No		No		INPUT
regs_tl_d_i.a_data[8]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_data[9]	No	No		No		INPUT
regs_tl_d_i.a_data[10]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_data[12:11]	No	No		No		INPUT
regs_tl_d_i.a_data[14:13]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_data[15]	No	No		No		INPUT
regs_tl_d_i.a_data[18:16]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_data[19]	No	No		No		INPUT
regs_tl_d_i.a_data[20]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_data[21]	No	No		No		INPUT
regs_tl_d_i.a_data[22]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_data[24:23]	No	No		No		INPUT
regs_tl_d_i.a_data[25]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_data[26]	No	No		No		INPUT
regs_tl_d_i.a_data[27]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_data[28]	No	No		No		INPUT
regs_tl_d_i.a_data[31:29]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_address[1:0]	No	No		No		INPUT
regs_tl_d_i.a_address[20:2]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[21]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_address[23:22]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[24]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[30]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_source[0]	Yes	Yes	*T26	Yes	T26	INPUT
regs_tl_d_i.a_source[5:1]	No	No		No		INPUT
regs_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_size[0]	No	No		No		INPUT
regs_tl_d_i.a_size[1]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_d_i.a_opcode[2]	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T26	Yes	T26	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T26	Yes	T26	OUTPUT
regs_tl_d_o.d_error	No	No		No		OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
regs_tl_d_o.d_user.rsp_intg[1:0]	Yes	Yes	T26	Yes	T26	OUTPUT
regs_tl_d_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T26	Yes	T26	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T26	Yes	T26	OUTPUT
regs_tl_d_o.d_sink	No	No		No		OUTPUT
regs_tl_d_o.d_source[0]	Yes	Yes	*T26	Yes	T26	OUTPUT
regs_tl_d_o.d_source[5:1]	No	No		No		OUTPUT
regs_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_size[0]	No	No		No		OUTPUT
regs_tl_d_o.d_size[1]	Yes	Yes	T26	Yes	T26	OUTPUT
regs_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T26	Yes	T26	OUTPUT
regs_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T26	Yes	T26	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_address[1:0]	No	No		No		INPUT
mem_tl_d_i.a_address[11:2]	Yes	Yes	T55,*T26,*T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_address[15:12]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_address[16]	Yes	Yes	*T55,*T26,*T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_address[31:17]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_source[4:0]	Yes	Yes	*T55,*T128,*T129	Yes	T55,T128,T129	INPUT
mem_tl_d_i.a_source[5]	No	No		No		INPUT
mem_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_size[0]	No	No		No		INPUT
mem_tl_d_i.a_size[1]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
mem_tl_d_i.a_opcode[2]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T17,T18,T44	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T55,T128,T129	Yes	T55,T128,T129	OUTPUT
mem_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T55,*T26,*T88	Yes	T55,T26,T88	OUTPUT
mem_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T55,*T26,*T88	Yes	T55,T26,T88	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T17,T18,T44	OUTPUT
mem_tl_d_o.d_sink	No	No		No		OUTPUT
mem_tl_d_o.d_source[4:0]	Yes	Yes	*T55,*T128,*T129	Yes	T55,T128,T129	OUTPUT
mem_tl_d_o.d_source[5]	No	No		No		OUTPUT
mem_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_size[0]	No	No		No		OUTPUT
mem_tl_d_o.d_size[1]	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	OUTPUT
mem_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T17,T18,T44	OUTPUT
mem_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T55,T26,T88	Yes	T55,T26,T88	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[0]	Yes	Yes	*T17,*T18,*T44	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
sba_tl_h_o.a_user.instr_type[3]	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_address[31:2]	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	OUTPUT
sba_tl_h_o.a_source[5:0]	No	No		No		OUTPUT
sba_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_size[0]	No	No		No		OUTPUT
sba_tl_h_o.a_size[1]	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_opcode[1:0]	No	No		No		OUTPUT
sba_tl_h_o.a_opcode[2]	Yes	Yes	T17,T18,T44	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	No	No		No		INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	INPUT
sba_tl_h_i.d_user.rsp_intg[1:0]	Yes	Yes	T53,T6,T26	Yes	T53,T6,T26	INPUT
sba_tl_h_i.d_user.rsp_intg[2]	No	No		No		INPUT
sba_tl_h_i.d_user.rsp_intg[5:3]	Yes	Yes	T53,*T55,T6	Yes	T53,T55,T6	INPUT
sba_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	INPUT
sba_tl_h_i.d_sink	No	No		No		INPUT
sba_tl_h_i.d_source[5:0]	No	No		No		INPUT
sba_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_size[0]	No	No		No		INPUT
sba_tl_h_i.d_size[1]	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	INPUT
sba_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T53,*T55,*T6	Yes	T53,T55,T6	INPUT
sba_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T53,T55,T6	Yes	T53,T55,T6	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T47,T170,T61	Yes	T47,T170,T61	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T47,T170,T61	Yes	T47,T170,T61	OUTPUT
jtag_i.tdi	Yes	Yes	T28,T53,T55	Yes	T28,T53,T55	INPUT
jtag_i.trst_n	Yes	Yes	T53,T6,T26	Yes	T28,T53,T55	INPUT
jtag_i.tms	Yes	Yes	T28,T53,T55	Yes	T28,T53,T55	INPUT
jtag_i.tck	Yes	Yes	T28,T53,T55	Yes	T28,T53,T55	INPUT
jtag_o.tdo_oe	Yes	Yes	T28,T53,T55	Yes	T28,T53,T55	OUTPUT
jtag_o.tdo	Yes	Yes	T28,T53,T55	Yes	T28,T53,T55	OUTPUT

*Tests covering at least one bit in the range