Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.49			89.49

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_aon_timer_aon	89.49			89.49

---

Module Instance : tb.dut.top_earlgrey.u_aon_timer_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.49			89.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.49			89.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	38	29	76.32
Total Bits	314	281	89.49
Total Bits 0->1	157	140	89.17
Total Bits 1->0	157	141	89.81

Ports	38	29	76.32
Port Bits	314	281	89.49
Port Bits 0->1	157	140	89.17
Port Bits 1->0	157	141	89.81

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_o.a_ready	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[0]	Yes	Yes	*T2,*T17,*T47	Yes	T2,T17,T47	OUTPUT
tl_o.d_user.data_intg[1]	No	Yes	*T264,*T258,*T265	No		OUTPUT
tl_o.d_user.data_intg[6:2]	Yes	Yes	T235,T236,T172	Yes	T235,T236,T172	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T17,T47,T4	Yes	T2,T17,T23	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T2,*T17,*T23	Yes	T2,T17,T23	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T17,T47,T4	Yes	T2,T17,T23	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T17,*T23	Yes	T2,T17,T23	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T35,T61,T62	Yes	T35,T61,T62	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T35,T61,T62	Yes	T35,T61,T62	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T17,T47,T48	Yes	T17,T47,T48	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T2,T211,T266	Yes	T2,T211,T266	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T235,T236,T237	Yes	T235,T236,T237	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T235,T236,T237	Yes	T235,T236,T237	OUTPUT
wkup_req_o	Yes	Yes	T2,T211,T266	Yes	T2,T211,T266	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T149,T99,T151	Yes	T149,T99,T151	OUTPUT
sleep_mode_i	Yes	Yes	T1,T2,T3	Yes	T2,T4,T5	INPUT

*Tests covering at least one bit in the range