Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.07			90.07
tb.dut.top_earlgrey.u_uart1	90.13			90.13
tb.dut.top_earlgrey.u_uart2	90.13			90.13
tb.dut.top_earlgrey.u_uart3	90.20			90.20

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_o.a_ready	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T122	Yes	T3,T4,T122	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T3,T4,T122	Yes	T3,T23,T4	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T21,T86	Yes	T3,T23,T4	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T4,T122	Yes	T3,T23,T4	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T88,*T3,*T23	Yes	T88,T3,T23	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T4,T21,T86	Yes	T3,T23,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T4,*T122	Yes	T3,T4,T122	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T281,T35,T61	Yes	T281,T35,T61	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T240,T160	Yes	T61,T160,T62	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T160,T62	Yes	T61,T240,T160	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T281,T35,T61	Yes	T281,T35,T61	OUTPUT
cio_rx_i	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T4,T122,T270	Yes	T4,T122,T270	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_break_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_timeout_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_o.a_ready	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T270	Yes	T3,T4,T270	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T3,T4,T270	Yes	T3,T23,T4	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T21,T86	Yes	T3,T23,T4	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T4,T270	Yes	T3,T23,T4	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T88,*T3,*T23	Yes	T88,T3,T23	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T4,T21,T86	Yes	T3,T23,T4	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T4,*T270	Yes	T3,T4,T270	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T281,T35,T61	Yes	T281,T35,T61	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T281,T35,T61	Yes	T281,T35,T61	OUTPUT
cio_rx_i	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T4,T270,T21	Yes	T4,T270,T21	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T270,T282	Yes	T3,T270,T282	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T270,T282	Yes	T3,T270,T282	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T270,T282	Yes	T3,T270,T282	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T270,T282	Yes	T3,T270,T282	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_break_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_timeout_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T3,T95,T35	Yes	T3,T95,T35	INPUT
tl_o.a_ready	Yes	Yes	T3,T95,T35	Yes	T3,T95,T35	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T3,T95,T139	Yes	T3,T95,T35	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T139,T88,*T272	Yes	T3,T95,T35	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T95,T139	Yes	T3,T95,T35	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T88,*T3,*T95	Yes	T88,T3,T95	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T139,T88,T272	Yes	T3,T95,T35	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T95,*T271	Yes	T3,T95,T271	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T95,T35	Yes	T3,T95,T35	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	OUTPUT
cio_rx_i	Yes	Yes	T95,T10,T11	Yes	T95,T10,T11	INPUT
cio_tx_o	Yes	Yes	T95,T271,T283	Yes	T95,T271,T283	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_break_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_timeout_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_o.a_ready	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T139,*T88,*T272	Yes	T3,T122,T94	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T88,*T3,*T122	Yes	T88,T3,T122	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T139,T88,T272	Yes	T3,T122,T94	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T122,*T94	Yes	T3,T122,T94	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T240,T62	Yes	T61,T62,T63	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T62,T63	Yes	T61,T240,T62	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	OUTPUT
cio_rx_i	Yes	Yes	T122,T94,T123	Yes	T122,T94,T123	INPUT
cio_tx_o	Yes	Yes	T122,T94,T123	Yes	T122,T94,T123	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_break_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_timeout_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T3,T35,T13	Yes	T3,T35,T13	INPUT
tl_o.a_ready	Yes	Yes	T3,T35,T13	Yes	T3,T35,T13	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T3,T13,T139	Yes	T3,T35,T13	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T139,T88,*T272	Yes	T3,T35,T13	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T13,T139	Yes	T3,T35,T13	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T88,*T3,*T13	Yes	T88,T3,T13	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T139,T88,T272	Yes	T3,T35,T13	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T13,*T92	Yes	T3,T13,T92	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T35,T13	Yes	T3,T35,T13	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	OUTPUT
cio_rx_i	Yes	Yes	T13,T10,T11	Yes	T13,T10,T11	INPUT
cio_tx_o	Yes	Yes	T13,T284,T285	Yes	T13,T284,T285	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_break_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_timeout_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T3,T92,T93	Yes	T3,T92,T93	OUTPUT

*Tests covering at least one bit in the range