Module Definition
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Module : prim_reg_cdc_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.49 94.00 86.05 73.91 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb 83.50 88.00 72.09 73.91 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
83.50 88.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL504488.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS1226466.67
CONT_ASSIGN13611100.00
ALWAYS1406583.33
ALWAYS15610990.00
CONT_ASSIGN18411100.00
ALWAYS188191789.47
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 0 1
130 1 1
133 0 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 0 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 0 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
211 0 1
212 0 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT28,T14,T26
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T14,T26
Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
83.50 72.09
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb

TotalCoveredPercent
Conditions433172.09
Logical433172.09
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT26
11CoveredT14,T27,T30 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T27,T30 

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT14,T26,T27
10Not Covered
11Not Covered 

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT14,T26,T27
101Not Covered
110CoveredT14,T26,T33
111Not Covered 

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T26,T33
10Not Covered 

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT14,T26,T27
11CoveredT14,T26,T27 

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT14,T27,T30
10Not Covered
11CoveredT14,T26,T33 

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT14,T27,T30 

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT14,T26,T33 

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT14,T26,T27
1Not Covered 

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT14,T26,T27
100CoveredT14,T26,T27 

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T27,T30
11CoveredT14,T26,T33 

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT14,T27,T30
1CoveredT1,T2,T3 

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT14,T27,T30
10CoveredT14,T26,T33
11CoveredT14,T27,T30 

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T27,T30
Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 17 73.91
IF 112 2 2 100.00
IF 122 4 2 50.00
IF 140 4 3 75.00
IF 156 6 5 83.33
CASE 198 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	112	if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	122	if ((!rst_dst_ni))
-2-:	124	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	130	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	140	if ((!rst_dst_ni))
-2-:	142	if (gen_wr_req.dst_lat_d)
-3-:	144	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T14,T26,T27
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	156	if ((!rst_dst_ni))
-2-:	158	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	160	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	162	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	164	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T14,T26,T27
0 0 1 - - Covered T14,T26,T33
0 0 0 1 - Covered T14,T27,T30
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	198	case (gen_wr_req.state_q)
-2-:	201	if (gen_wr_req.dst_req)
-3-:	205	if (dst_update)
-4-:	208	if ((dst_qs_o != dst_qs_i))
-5-:	218	if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T14,T26,T33
StIdle 0 1 - - Covered T14,T27,T30
StIdle 0 0 1 - Not Covered
StIdle 0 0 0 - Covered T14,T26,T27
StWait - - - 1 Covered T14,T26,T27
StWait - - - 0 Covered T14,T26,T27
default - - - - Not Covered

Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 1321993 15 0 917
gen_wr_req.HwIdSelCheck_A 1321993 15 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1321993 15 0 917
T14 610 6 0 1
T27 0 1 0 0
T30 0 1 0 0
T32 0 1 0 0
T33 0 3 0 0
T34 0 3 0 0
T77 1043 0 0 1
T78 917 0 0 1
T79 1587 0 0 0
T80 1110 0 0 1
T81 637 0 0 1
T82 679 0 0 1
T83 493 0 0 1
T84 613 0 0 1
T85 1532 0 0 1
T199 0 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1321993 15 0 0
T14 610 6 0 0
T27 0 1 0 0
T30 0 1 0 0
T32 0 1 0 0
T33 0 3 0 0
T34 0 3 0 0
T77 1043 0 0 0
T78 917 0 0 0
T79 1587 0 0 0
T80 1110 0 0 0
T81 637 0 0 0
T82 679 0 0 0
T83 493 0 0 0
T84 613 0 0 0
T85 1532 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%