Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.73			89.73

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	89.73			89.73

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.73			89.73

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.73			89.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	368	65.48
Total Bits	7060	6335	89.73
Total Bits 0->1	3530	3167	89.72
Total Bits 1->0	3530	3168	89.75

Ports	562	368	65.48
Port Bits	7060	6335	89.73
Port Bits 0->1	3530	3167	89.72
Port Bits 1->0	3530	3168	89.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_main_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_main_i.a_opcode[1]	No	No		No		INPUT
tl_main_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T136,T137,T138	Yes	T136,T137,T138	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	No	No		No		OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_uart0_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_uart0_i.d_error	No	No		No		INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T3,T4,T270	Yes	T3,T4,T270	INPUT
tl_uart0_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T4,T270	Yes	T3,T23,T4	INPUT
tl_uart0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart0_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T21,T86	Yes	T3,T23,T4	INPUT
tl_uart0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T3,T4,T270	Yes	T3,T23,T4	INPUT
tl_uart0_i.d_sink	No	No		No		INPUT
tl_uart0_i.d_source[1:0]	Yes	Yes	*T88,*T3,*T23	Yes	T88,T3,T23	INPUT
tl_uart0_i.d_source[5:2]	No	No		No		INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[0]	No	No		No		INPUT
tl_uart0_i.d_size[1]	Yes	Yes	T4,T21,T86	Yes	T3,T23,T4	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T3,*T4,*T270	Yes	T3,T4,T270	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T3,T23,T4	Yes	T3,T23,T4	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_uart1_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T3,T95,T35	Yes	T3,T95,T35	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T3,T95,T35	Yes	T3,T95,T35	INPUT
tl_uart1_i.d_error	No	No		No		INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T3,T95,T271	Yes	T3,T95,T271	INPUT
tl_uart1_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T95,T139	Yes	T3,T95,T35	INPUT
tl_uart1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T139,T88,*T272	Yes	T3,T95,T35	INPUT
tl_uart1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T3,T95,T139	Yes	T3,T95,T35	INPUT
tl_uart1_i.d_sink	No	No		No		INPUT
tl_uart1_i.d_source[1:0]	Yes	Yes	*T88,*T3,*T95	Yes	T88,T3,T95	INPUT
tl_uart1_i.d_source[5:2]	No	No		No		INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[0]	No	No		No		INPUT
tl_uart1_i.d_size[1]	Yes	Yes	T139,T88,T272	Yes	T3,T95,T35	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T3,*T95,*T271	Yes	T3,T95,T271	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T3,T95,T35	Yes	T3,T95,T35	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_uart2_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_uart2_i.d_error	No	No		No		INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_uart2_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_uart2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T139,*T88,*T272	Yes	T3,T122,T94	INPUT
tl_uart2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_uart2_i.d_sink	No	No		No		INPUT
tl_uart2_i.d_source[1:0]	Yes	Yes	*T88,*T3,*T122	Yes	T88,T3,T122	INPUT
tl_uart2_i.d_source[5:2]	No	No		No		INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[0]	No	No		No		INPUT
tl_uart2_i.d_size[1]	Yes	Yes	T139,T88,T272	Yes	T3,T122,T94	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T3,*T122,*T94	Yes	T3,T122,T94	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T3,T122,T94	Yes	T3,T122,T94	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_uart3_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_uart3_o.a_opcode[1]	No	No		No		OUTPUT
tl_uart3_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T3,T35,T13	Yes	T3,T35,T13	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T3,T35,T13	Yes	T3,T35,T13	INPUT
tl_uart3_i.d_error	No	No		No		INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T3,T13,T92	Yes	T3,T13,T92	INPUT
tl_uart3_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T13,T139	Yes	T3,T35,T13	INPUT
tl_uart3_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_uart3_i.d_user.rsp_intg[5:4]	Yes	Yes	*T139,T88,*T272	Yes	T3,T35,T13	INPUT
tl_uart3_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T3,T13,T139	Yes	T3,T35,T13	INPUT
tl_uart3_i.d_sink	No	No		No		INPUT
tl_uart3_i.d_source[1:0]	Yes	Yes	*T88,*T3,*T13	Yes	T88,T3,T13	INPUT
tl_uart3_i.d_source[5:2]	No	No		No		INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[0]	No	No		No		INPUT
tl_uart3_i.d_size[1]	Yes	Yes	T139,T88,T272	Yes	T3,T35,T13	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T3,*T13,*T92	Yes	T3,T13,T92	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T3,T35,T13	Yes	T3,T35,T13	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T172,T87,T212	Yes	T172,T87,T212	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T172,T87,T212	Yes	T172,T87,T212	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_i2c0_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c0_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T35,T139,T172	Yes	T35,T139,T172	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T35,T139,T172	Yes	T35,T139,T172	INPUT
tl_i2c0_i.d_error	No	No		No		INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T172,T212,T174	Yes	T172,T212,T174	INPUT
tl_i2c0_i.d_user.rsp_intg[1:0]	Yes	Yes	T139,T172,T87	Yes	T35,T139,T172	INPUT
tl_i2c0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T139,T87,T144	Yes	T35,T139,T172	INPUT
tl_i2c0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T139,T172,T87	Yes	T35,T139,T172	INPUT
tl_i2c0_i.d_sink	No	No		No		INPUT
tl_i2c0_i.d_source[0]	No	No		No		INPUT
tl_i2c0_i.d_source[1]	Yes	Yes	*T139,*T172,*T87	Yes	T139,T172,T87	INPUT
tl_i2c0_i.d_source[5:2]	No	No		No		INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[0]	No	No		No		INPUT
tl_i2c0_i.d_size[1]	Yes	Yes	T139,T87,T144	Yes	T35,T139,T172	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T172,*T87,*T212	Yes	T172,T87,T212	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T35,T139,T172	Yes	T35,T139,T172	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T65,T172,T87	Yes	T65,T172,T87	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c1_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T65,T172,T87	Yes	T65,T172,T87	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_i2c1_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c1_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T65,T35,T139	Yes	T65,T35,T139	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T65,T35,T139	Yes	T65,T35,T139	INPUT
tl_i2c1_i.d_error	No	No		No		INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T65,T172,T87	Yes	T65,T172,T87	INPUT
tl_i2c1_i.d_user.rsp_intg[1:0]	Yes	Yes	T65,T139,T172	Yes	T65,T35,T139	INPUT
tl_i2c1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c1_i.d_user.rsp_intg[5:4]	Yes	Yes	*T139,T87,T144	Yes	T65,T35,T139	INPUT
tl_i2c1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T65,T139,T172	Yes	T65,T35,T139	INPUT
tl_i2c1_i.d_sink	No	No		No		INPUT
tl_i2c1_i.d_source[0]	No	No		No		INPUT
tl_i2c1_i.d_source[1]	Yes	Yes	*T65,*T172,*T87	Yes	T65,T172,T87	INPUT
tl_i2c1_i.d_source[5:2]	No	No		No		INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[0]	No	No		No		INPUT
tl_i2c1_i.d_size[1]	Yes	Yes	T139,T87,T144	Yes	T65,T35,T139	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T65,*T172,*T87	Yes	T65,T172,T87	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T65,T35,T139	Yes	T65,T35,T139	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T214,T172,T87	Yes	T214,T172,T87	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_i2c2_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T214,T172,T87	Yes	T214,T172,T87	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_i2c2_o.a_opcode[1]	No	No		No		OUTPUT
tl_i2c2_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T35,T214,T139	Yes	T35,T214,T139	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T35,T214,T139	Yes	T35,T214,T139	INPUT
tl_i2c2_i.d_error	No	No		No		INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T214,T172,T174	Yes	T214,T172,T174	INPUT
tl_i2c2_i.d_user.rsp_intg[1:0]	Yes	Yes	T214,T139,T172	Yes	T35,T214,T139	INPUT
tl_i2c2_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_i2c2_i.d_user.rsp_intg[5:4]	Yes	Yes	*T139,T87,T144	Yes	T35,T214,T139	INPUT
tl_i2c2_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T214,T139,T172	Yes	T35,T214,T139	INPUT
tl_i2c2_i.d_sink	No	No		No		INPUT
tl_i2c2_i.d_source[0]	No	No		No		INPUT
tl_i2c2_i.d_source[1]	Yes	Yes	*T214,*T172,*T87	Yes	T214,T172,T87	INPUT
tl_i2c2_i.d_source[5:2]	No	No		No		INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[0]	No	No		No		INPUT
tl_i2c2_i.d_size[1]	Yes	Yes	T139,T87,T144	Yes	T35,T214,T139	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T214,*T172,*T87	Yes	T214,T172,T87	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T35,T214,T139	Yes	T35,T214,T139	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T213,T26,T143	Yes	T213,T26,T143	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pattgen_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T213,T26,T143	Yes	T213,T26,T143	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_pattgen_o.a_opcode[1]	No	No		No		OUTPUT
tl_pattgen_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T213,T35,T26	Yes	T213,T35,T26	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T213,T35,T26	Yes	T213,T35,T26	INPUT
tl_pattgen_i.d_error	No	No		No		INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T213,T26,T143	Yes	T213,T26,T143	INPUT
tl_pattgen_i.d_user.rsp_intg[1:0]	Yes	Yes	T213,T26,T143	Yes	T213,T35,T26	INPUT
tl_pattgen_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pattgen_i.d_user.rsp_intg[5:4]	Yes	Yes	T26,T40,*T213	Yes	T213,T35,T26	INPUT
tl_pattgen_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T213,T26,T143	Yes	T213,T35,T26	INPUT
tl_pattgen_i.d_sink	No	No		No		INPUT
tl_pattgen_i.d_source[1:0]	Yes	Yes	*T26,*T40,*T213	Yes	T26,T40,T213	INPUT
tl_pattgen_i.d_source[5:2]	No	No		No		INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[0]	No	No		No		INPUT
tl_pattgen_i.d_size[1]	Yes	Yes	T26,T40	Yes	T213,T35,T26	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T213,*T26,*T143	Yes	T213,T26,T143	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T213,T35,T26	Yes	T213,T35,T26	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T26,T273,T107	Yes	T26,T273,T107	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T26,T273,T107	Yes	T26,T273,T107	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_pwm_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwm_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T35,T26,T273	Yes	T35,T26,T273	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T35,T26,T273	Yes	T35,T26,T273	INPUT
tl_pwm_aon_i.d_error	No	No		No		INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T26,T273,T107	Yes	T26,T273,T107	INPUT
tl_pwm_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T26,T273,T107	Yes	T35,T26,T273	INPUT
tl_pwm_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwm_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T26,*T273,*T107	Yes	T35,T26,T273	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T26,T273,T107	Yes	T35,T26,T273	INPUT
tl_pwm_aon_i.d_sink	No	No		No		INPUT
tl_pwm_aon_i.d_source[1:0]	Yes	Yes	*T26,*T273,*T107	Yes	T26,T273,T107	INPUT
tl_pwm_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[0]	No	No		No		INPUT
tl_pwm_aon_i.d_size[1]	Yes	Yes	T26	Yes	T35,T26,T273	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T26,*T273,*T107	Yes	T26,T273,T107	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T35,T26,T273	Yes	T35,T26,T273	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T24,T25	Yes	T4,T24,T25	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_gpio_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_gpio_o.a_opcode[1]	No	No		No		OUTPUT
tl_gpio_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	No	No		No		INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T172,T174,T260	Yes	T172,T174,T260	INPUT
tl_gpio_i.d_user.rsp_intg[1:0]	Yes	Yes	T172,T174,T107	Yes	T35,T172,T14	INPUT
tl_gpio_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_gpio_i.d_user.rsp_intg[5:4]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T172,T174,T107	Yes	T35,T172,T14	INPUT
tl_gpio_i.d_sink	No	No		No		INPUT
tl_gpio_i.d_source[0]	No	No		No		INPUT
tl_gpio_i.d_source[1]	Yes	Yes	*T16,*T17,*T18	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_source[5:2]	No	No		No		INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[0]	No	No		No		INPUT
tl_gpio_i.d_size[1]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T95,T87,T96	Yes	T95,T87,T96	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_device_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T95,T87,T96	Yes	T95,T87,T96	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_spi_device_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_device_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T95,T35,T87	Yes	T95,T35,T87	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T95,T35,T87	Yes	T95,T35,T87	INPUT
tl_spi_device_i.d_error	No	No		No		INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T95,T87,T96	Yes	T95,T87,T96	INPUT
tl_spi_device_i.d_user.rsp_intg[1:0]	Yes	Yes	T95,T87,T96	Yes	T95,T87,T96	INPUT
tl_spi_device_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_device_i.d_user.rsp_intg[5:4]	Yes	Yes	T95,T87,T96	Yes	T95,T35,T87	INPUT
tl_spi_device_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T95,T35,T87	Yes	T95,T87,T96	INPUT
tl_spi_device_i.d_sink	No	No		No		INPUT
tl_spi_device_i.d_source[1:0]	Yes	Yes	*T88,*T95,*T87	Yes	T88,T95,T35	INPUT
tl_spi_device_i.d_source[5:2]	No	No		No		INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[0]	No	No		No		INPUT
tl_spi_device_i.d_size[1]	Yes	Yes	T95,T87,T96	Yes	T95,T35,T87	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T95,*T35,*T87	Yes	T95,T87,T96	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T95,T35,T87	Yes	T95,T35,T87	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T267,T268,T233	Yes	T267,T268,T233	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_timer_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T267,T268,T233	Yes	T267,T268,T233	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_rv_timer_o.a_opcode[1]	No	No		No		OUTPUT
tl_rv_timer_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T35,T267,T268	Yes	T35,T267,T268	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T35,T267,T268	Yes	T35,T267,T268	INPUT
tl_rv_timer_i.d_error	No	No		No		INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T267,T268,T233	Yes	T267,T268,T233	INPUT
tl_rv_timer_i.d_user.rsp_intg[1:0]	Yes	Yes	T267,T268,T233	Yes	T35,T267,T268	INPUT
tl_rv_timer_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_timer_i.d_user.rsp_intg[5:4]	Yes	Yes	T107,T73,T88	Yes	T35,T267,T268	INPUT
tl_rv_timer_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T267,T268,T233	Yes	T35,T267,T268	INPUT
tl_rv_timer_i.d_sink	No	No		No		INPUT
tl_rv_timer_i.d_source[1:0]	Yes	Yes	*T88,*T267,*T268	Yes	T88,T267,T268	INPUT
tl_rv_timer_i.d_source[5:2]	No	No		No		INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[0]	No	No		No		INPUT
tl_rv_timer_i.d_size[1]	Yes	Yes	T107,T73,T88	Yes	T35,T267,T268	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T267,*T268,*T233	Yes	T267,T268,T233	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T35,T267,T268	Yes	T35,T267,T268	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T23,T4	Yes	T2,T23,T4	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T23,T4	Yes	T2,T23,T4	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_pwrmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T2,T23,T4	Yes	T2,T23,T4	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T2,T23,T4	Yes	T2,T23,T4	INPUT
tl_pwrmgr_aon_i.d_error	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T149,T5	Yes	T2,T149,T5	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T2,T23,T4	Yes	T2,T23,T4	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T4,T5,*T100	Yes	T2,T23,T4	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T23,T4	Yes	T2,T23,T4	INPUT
tl_pwrmgr_aon_i.d_sink	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[1:0]	Yes	Yes	*T26,*T2,*T23	Yes	T26,T2,T23	INPUT
tl_pwrmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_pwrmgr_aon_i.d_size[1]	Yes	Yes	T4,T5,T100	Yes	T2,T23,T4	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T23,*T4	Yes	T2,T23,T4	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T2,T23,T4	Yes	T2,T23,T4	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_rstmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_rstmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[1:0]	Yes	Yes	*T26,*T16,*T17	Yes	T26,T1,T2	INPUT
tl_rstmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_rstmgr_aon_i.d_size[1]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T54,T149,T274	Yes	T54,T149,T274	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T54,T149,T101	Yes	T54,T149,T101	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_clkmgr_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_clkmgr_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T54,T274,T122	Yes	T54,T274,T6	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	*T16,*T17,*T18	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[0]	No	No		Yes	T6,T275,T276	INPUT
tl_clkmgr_aon_i.d_source[1]	Yes	Yes	*T16,*T17,*T18	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_source[5:2]	No	No		No		INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[0]	No	No		No		INPUT
tl_clkmgr_aon_i.d_size[1]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T54,*T149,*T274	Yes	T54,T149,T274	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_pinmux_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_pinmux_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	No	No		No		INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[2]	No	No		No		INPUT
tl_pinmux_aon_i.d_user.rsp_intg[5:3]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	No	No		No		INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T26,*T40,*T1	Yes	T26,T40,T1	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_otp_ctrl__core_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[1:0]	Yes	Yes	*T6,*T26,*T37	Yes	T6,T26,T37	INPUT
tl_otp_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__core_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T16,*T18,*T44	Yes	T16,T18,T44	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T26,T40	Yes	T26,T40	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T26,T40	Yes	T26,T40	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_otp_ctrl__prim_o.a_opcode[1]	No	No		No		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T26,T40	Yes	T26,T40	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T17,T18,T44	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T26,T40	Yes	T26,T40	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[2:0]	Yes	Yes	*T26,*T40,*T1	Yes	T26,T40,T17	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[5:4]	Yes	Yes	*T26,*T40,*T17	Yes	T26,T40,T1	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T17,T18,T44	INPUT
tl_otp_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[0]	Yes	Yes	*T26,*T40	Yes	T26,T40	INPUT
tl_otp_ctrl__prim_i.d_source[5:1]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[0]	No	No		No		INPUT
tl_otp_ctrl__prim_i.d_size[1]	Yes	Yes	T26,T40	Yes	T26,T40	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T17,T18,T44	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T26,T40	Yes	T26,T40	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T16,T23,T4	Yes	T16,T23,T4	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T16,T23,T4	Yes	T16,T23,T4	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_lc_ctrl_o.a_opcode[1]	No	No		No		OUTPUT
tl_lc_ctrl_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T16,T23,T4	Yes	T16,T23,T4	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T16,T23,T4	Yes	T16,T23,T4	INPUT
tl_lc_ctrl_i.d_error	No	No		No		INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T23,T4,T55	Yes	T23,T4,T55	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[1:0]	Yes	Yes	T46,T184,T80	Yes	T46,T35,T184	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_user.rsp_intg[5:4]	Yes	Yes	T16,T4,T55	Yes	T16,T23,T4	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T16,T23,T4	Yes	T16,T23,T4	INPUT
tl_lc_ctrl_i.d_sink	No	No		No		INPUT
tl_lc_ctrl_i.d_source[1:0]	Yes	Yes	*T55,*T128,*T129	Yes	T55,T128,T129	INPUT
tl_lc_ctrl_i.d_source[5:2]	No	No		No		INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[0]	No	No		No		INPUT
tl_lc_ctrl_i.d_size[1]	Yes	Yes	T16,T4,T55	Yes	T16,T23,T4	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T16,*T4,*T55	Yes	T16,T23,T4	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T16,T23,T4	Yes	T16,T23,T4	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T104,T143,T116	Yes	T104,T143,T116	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T104,T143,T116	Yes	T35,T104,T143	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[1:0]	Yes	Yes	*T88,*T16,*T17	Yes	T88,T1,T2	INPUT
tl_sensor_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sensor_ctrl_aon_i.d_size[1]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_alert_handler_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_alert_handler_o.a_opcode[1]	No	No		No		OUTPUT
tl_alert_handler_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_error	No	No		No		INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_user.rsp_intg[1:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_alert_handler_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T47,*T4	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_sink	No	No		No		INPUT
tl_alert_handler_i.d_source[0]	No	No		No		INPUT
tl_alert_handler_i.d_source[1]	Yes	Yes	*T2,*T17,*T23	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_source[5:2]	No	No		No		INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[0]	No	No		No		INPUT
tl_alert_handler_i.d_size[1]	Yes	Yes	T17,T47,T4	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T2,*T17,*T47	Yes	T2,T17,T23	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T23,T4,T6	Yes	T23,T4,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T23,T4,T6	Yes	T23,T4,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T23,T4,T6	Yes	T23,T4,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T23,T4,T6	Yes	T23,T4,T6	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T105,*T157,T277	Yes	T105,T157,T277	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T4,T21,T22	Yes	T23,T4,T6	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T4,*T21,*T22	Yes	T23,T4,T6	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T4,T21,T22	Yes	T23,T4,T6	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[1:0]	Yes	Yes	*T88,*T4,*T21	Yes	T88,T23,T4	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1]	Yes	Yes	T4,T21,T22	Yes	T23,T4,T6	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T105,*T157,*T277	Yes	T105,T157,T277	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T23,T4,T6	Yes	T23,T4,T6	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T16,T17,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T2,T16,T17	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[1:0]	Yes	Yes	*T127,*T130,*T131	Yes	T127,T130,T131	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_aon_timer_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_aon_timer_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_aon_timer_aon_i.d_error	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.data_intg[0]	Yes	Yes	*T2,*T17,*T47	Yes	T2,T17,T47	INPUT
tl_aon_timer_aon_i.d_user.data_intg[1]	No	Yes	*T264,*T258,*T265	No		INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:2]	Yes	Yes	T235,T236,T172	Yes	T235,T236,T172	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T17,T47,T4	Yes	T2,T17,T23	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_aon_timer_aon_i.d_sink	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[0]	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[1]	Yes	Yes	*T2,*T17,*T23	Yes	T2,T17,T23	INPUT
tl_aon_timer_aon_i.d_source[5:2]	No	No		No		INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[0]	No	No		No		INPUT
tl_aon_timer_aon_i.d_size[1]	Yes	Yes	T17,T47,T4	Yes	T2,T17,T23	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T2,*T17,*T23	Yes	T2,T17,T23	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T2,T17,T23	Yes	T2,T17,T23	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T28,T5	Yes	T3,T28,T5	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T3,T28,T5	Yes	T3,T28,T5	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T3,T28,T5	Yes	T3,T28,T5	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T3,T28,T5	Yes	T3,T28,T5	INPUT
tl_sysrst_ctrl_aon_i.d_error	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T5,T15	Yes	T3,T5,T15	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T3,T28,T5	Yes	T3,T28,T5	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T28,T5,T100	Yes	T3,T28,T5	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T28,T5,T15	Yes	T3,T28,T5	INPUT
tl_sysrst_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[1:0]	Yes	Yes	*T88,*T3,*T5	Yes	T88,T3,T28	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_sysrst_ctrl_aon_i.d_size[1]	Yes	Yes	T28,T5,T100	Yes	T3,T28,T5	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T3,*T5,*T15	Yes	T3,T28,T5	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T3,T28,T5	Yes	T3,T28,T5	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T28,T172,T104	Yes	T28,T172,T104	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T28,T172,T104	Yes	T28,T172,T104	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_adc_ctrl_aon_o.a_opcode[1]	No	No		No		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T28,T35,T172	Yes	T28,T35,T172	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T28,T35,T172	Yes	T28,T35,T172	INPUT
tl_adc_ctrl_aon_i.d_error	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[4:0]	Yes	Yes	*T172,T104,*T174	Yes	T28,T172,T104	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[5]	No	Yes	*T28,*T29,*T108	No		INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6]	Yes	Yes	T104,T108,T109	Yes	T104,T108,T109	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[1:0]	Yes	Yes	T28,T172,T104	Yes	T28,T35,T172	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[5:4]	Yes	Yes	T28,T29,*T31	Yes	T28,T35,T172	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T28,T104,T107	Yes	T28,T35,T172	INPUT
tl_adc_ctrl_aon_i.d_sink	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[1]	Yes	Yes	*T104,*T107,*T73	Yes	T28,T172,T104	INPUT
tl_adc_ctrl_aon_i.d_source[5:2]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[0]	No	No		No		INPUT
tl_adc_ctrl_aon_i.d_size[1]	Yes	Yes	T28,T29,T31	Yes	T28,T35,T172	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T172,*T104,*T174	Yes	T28,T172,T104	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T28,T35,T172	Yes	T28,T35,T172	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_ast_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T55,*T6,*T26	Yes	T55,T6,T26	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
tl_ast_o.a_opcode[1]	No	No		No		OUTPUT
tl_ast_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	No	No		No		INPUT
tl_ast_i.d_user.data_intg[6:0]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[1:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_ast_i.d_user.rsp_intg[4]	Yes	Yes	*T16,*T17,*T18	Yes	T1,T2,T3	INPUT
tl_ast_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	No	No		No		INPUT
tl_ast_i.d_source[0]	No	No		No		INPUT
tl_ast_i.d_source[5:1]	Yes	Yes	*T10,*T11,T12	Yes	T10,T11,T12	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[0]	No	No		No		INPUT
tl_ast_i.d_size[1]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	No	No		No		INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range