Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.61 95.61

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 92.82 92.82
tb.dut.top_earlgrey.u_edn0 95.51 95.51


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.82 92.82


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.82 92.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.74 90.68 90.55 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.51 95.51


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.51 95.51


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.74 90.68 90.55 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 63 80.77
Total Bits 1206 1153 95.61
Total Bits 0->1 603 578 95.85
Total Bits 1->0 603 575 95.36

Ports 78 63 80.77
Port Bits 1206 1153 95.61
Port Bits 0->1 603 578 95.85
Port Bits 1->0 603 575 95.36

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T16,T17,T18 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T16,T17,T18 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T16,*T17,*T18 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T16,T17,T18 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T16,*T17,*T18 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T16,T17,T18 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T16,T18,T44 Yes T16,T18,T44 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T347,T363,T364 Yes T347,T363,T364 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T16,T18,T44 Yes T16,T18,T44 OUTPUT
edn_o[0].edn_fips Yes Yes T156,T113,T83 Yes T110,T102,T103 OUTPUT
edn_o[0].edn_ack Yes Yes T16,T18,T44 Yes T16,T18,T44 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T102,T178,T103 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T65,T18,T66 Yes T1,T2,T65 OUTPUT
edn_o[2].edn_fips Yes Yes T113,T114,T115 Yes T102,T103,T113 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T347,T363,T364 Yes T347,T363,T364 OUTPUT
edn_o[3].edn_fips No No Yes T347,T363,T364 OUTPUT
edn_o[3].edn_ack Yes Yes T347,T363,T364 Yes T347,T363,T364 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T17,T18,T44 Yes T1,T2,T3 OUTPUT
edn_o[4].edn_fips No No Yes T103,T365 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T366,T367,T368 Yes T347,T369,T363 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T156,T113,T83 Yes T110,T102,T178 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T2,T16,T17 Yes T1,T2,T16 OUTPUT
edn_o[7].edn_fips Yes Yes T156,T113,T83 Yes T156,T113,T83 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T156,T83,T370 Yes T110,T102,T178 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T111,T113,T369 Yes T111,T113,T369 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T111,T35,T61 Yes T111,T35,T61 INPUT
alert_rx_i[0].ping_n Yes Yes T61,T160,T62 Yes T61,T160,T62 INPUT
alert_rx_i[0].ping_p Yes Yes T61,T160,T62 Yes T61,T160,T62 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T48,T371,T35 Yes T48,T371,T35 INPUT
alert_rx_i[1].ping_n Yes Yes T61,T320,T62 Yes T61,T62,T63 INPUT
alert_rx_i[1].ping_p Yes Yes T61,T62,T63 Yes T61,T320,T62 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T111,T35,T61 Yes T111,T35,T61 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T48,T371,T35 Yes T48,T371,T35 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T110,T172,T174 Yes T110,T172,T174 OUTPUT
intr_edn_fatal_err_o Yes Yes T172,T174,T175 Yes T172,T174,T175 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 710 659 92.82
Total Bits 0->1 355 330 92.96
Total Bits 1->0 355 329 92.68

Ports 50 37 74.00
Port Bits 710 659 92.82
Port Bits 0->1 355 330 92.96
Port Bits 1->0 355 329 92.68

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T16,T17,T18 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T16,T17,T18 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_mask[3:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_valid Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_o.a_ready Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T104,*T155,*T121 Yes T110,T111,T102 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T110,T111,T156 Yes T110,T111,T102 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T104,T155,T121 Yes T110,T111,T102 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
edn_i[0].edn_req Yes Yes T110,T102,T103 Yes T110,T102,T103 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T110,T102,T103 Yes T110,T102,T103 OUTPUT
edn_o[0].edn_fips Yes Yes T156,T113,T83 Yes T110,T102,T103 OUTPUT
edn_o[0].edn_ack Yes Yes T110,T102,T103 Yes T110,T102,T103 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
csrng_cmd_i.genbits_fips No No Yes T156,T83,T370 INPUT
csrng_cmd_i.genbits_valid Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T113,T114,T366 Yes T113,T114,T366 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T35,T61,T160 Yes T35,T61,T160 INPUT
alert_rx_i[0].ping_n Yes Yes T61,T160,T62 Yes T61,T160,T62 INPUT
alert_rx_i[0].ping_p Yes Yes T61,T160,T62 Yes T61,T160,T62 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T35,T61,T240 Yes T35,T61,T240 INPUT
alert_rx_i[1].ping_n Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_rx_i[1].ping_p Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T35,T61,T160 Yes T35,T61,T160 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T35,T61,T240 Yes T35,T61,T240 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T110,T172,T174 Yes T110,T172,T174 OUTPUT
intr_edn_fatal_err_o Yes Yes T172,T174,T175 Yes T172,T174,T175 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 62 79.49
Total Bits 1204 1150 95.51
Total Bits 0->1 602 577 95.85
Total Bits 1->0 602 573 95.18

Ports 78 62 79.49
Port Bits 1204 1150 95.51
Port Bits 0->1 602 577 95.85
Port Bits 1->0 602 573 95.18

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T16,T17,T18 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T110,T111,T102 Yes T110,T111,T102 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T110,T111,T102 Yes T110,T111,T102 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T16,T17,T18 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T16,*T17,*T18 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T16,T17,T18 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T16,*T17,*T18 Yes T1,T2,T3 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T16,T17,T18 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T110,*T111,*T102 Yes T110,T111,T102 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T16,T18,T44 Yes T16,T18,T44 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T347,T363,T364 Yes T347,T363,T364 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T16,T18,T44 Yes T16,T18,T44 OUTPUT
edn_o[0].edn_fips No No Yes T347,T372,T363 OUTPUT
edn_o[0].edn_ack Yes Yes T16,T18,T44 Yes T16,T18,T44 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T102,T178,T103 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T65,T18,T66 Yes T1,T2,T65 OUTPUT
edn_o[2].edn_fips Yes Yes T113,T114,T115 Yes T102,T103,T113 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T347,T363,T364 Yes T347,T363,T364 OUTPUT
edn_o[3].edn_fips No No Yes T347,T363,T364 OUTPUT
edn_o[3].edn_ack Yes Yes T347,T363,T364 Yes T347,T363,T364 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T17,T18,T44 Yes T1,T2,T3 OUTPUT
edn_o[4].edn_fips No No Yes T103,T365 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T366,T367,T368 Yes T347,T369,T363 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T156,T113,T83 Yes T110,T102,T178 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T2,T16,T17 Yes T1,T2,T16 OUTPUT
edn_o[7].edn_fips Yes Yes T156,T113,T83 Yes T156,T113,T83 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T156,T83,T370 Yes T110,T102,T178 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T111,T113,T369 Yes T111,T113,T369 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T111,T35,T61 Yes T111,T35,T61 INPUT
alert_rx_i[0].ping_n Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_rx_i[0].ping_p Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T48,T371,T35 Yes T48,T371,T35 INPUT
alert_rx_i[1].ping_n Yes Yes T61,T320,T62 Yes T61,T62,T63 INPUT
alert_rx_i[1].ping_p Yes Yes T61,T62,T63 Yes T61,T320,T62 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T111,T35,T61 Yes T111,T35,T61 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T48,T371,T35 Yes T48,T371,T35 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T110,T172,T174 Yes T110,T172,T174 OUTPUT
intr_edn_fatal_err_o Yes Yes T172,T174,T175 Yes T172,T174,T175 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%