CHIP Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.290m	2.828ms	3	3	100.00
		chip_sw_example_rom	2.266m	2.410ms	3	3	100.00
		chip_sw_example_manufacturer	5.556m	2.933ms	3	3	100.00
		chip_sw_example_concurrency	4.339m	2.753ms	3	3	100.00
		chip_sw_uart_smoketest_signed	35.210m	8.710ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.560m	4.081ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.560m	4.081ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.560m	4.081ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	15.560m	5.482ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	15.560m	5.482ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	20.366m	5.606ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	17.447m	5.952ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	17.456m	5.411ms	5	5	100.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.264h	22.747ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	52.125m	14.261ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	35.623m	23.711ms	5	5	100.00
V1		TOTAL			68	223	30.49
V2	chip_pin_mux	chip_padctrl_attributes	5.863m	5.237ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.863m	5.237ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.870m	3.285ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.282m	4.707ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.604m	3.414ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	13.075m	7.506ms	5	5	100.00
		chip_tap_straps_testunlock0	8.867m	5.574ms	5	5	100.00
		chip_tap_straps_rma	18.642m	8.669ms	5	5	100.00
		chip_tap_straps_prod	28.399m	14.051ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.100m	2.744ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	23.098m	7.929ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.624m	6.333ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.624m	6.333ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.461m	3.434ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	7.115m	3.277ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.330m	4.007ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	35.566m	25.151ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_sysrst_ctrl_reset	35.566m	25.151ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	35.566m	25.151ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.052h	20.415ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.052h	20.415ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.539m	5.037ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.184m	19.028ms	3	3	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.334m	7.902ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	13.327m	11.359ms	3	3	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	15.604m	5.562ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.088m	6.329ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.049h	18.905ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.483m	3.269ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.923m	5.887ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.732m	3.139ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.266m	3.934ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.698m	3.281ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.563m	5.653ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.378m	3.061ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.494m	3.339ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	18.787m	7.047ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	18.787m	7.047ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.416m	4.988ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.217m	2.845ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.416m	4.988ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.990m	2.335ms	3	3	100.00
		chip_sw_aes_smoketest	5.990m	2.794ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.767m	3.394ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.018m	2.944ms	3	3	100.00
		chip_sw_csrng_smoketest	5.065m	3.642ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.267m	4.370ms	3	3	100.00
		chip_sw_gpio_smoketest	5.263m	2.828ms	3	3	100.00
		chip_sw_hmac_smoketest	7.563m	3.095ms	3	3	100.00
		chip_sw_kmac_smoketest	5.396m	2.935ms	3	3	100.00
		chip_sw_otbn_smoketest	39.946m	8.578ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.613m	3.112ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.366m	4.268ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.869m	5.722ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.274m	3.083ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.925m	2.812ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.667m	2.765ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	3.990m	2.407ms	3	3	100.00
		chip_sw_uart_smoketest	4.925m	2.924ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.078m	5.543ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	35.210m	8.710ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.663h	73.771ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.692m	9.109ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	35.642m	16.818ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.769m	4.376ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	9.072m	10.201ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.953h	61.279ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.304h	66.961ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.692m	9.109ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	53.222m	22.751ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.637m	8.929ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	27.872m	7.234ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	32.862m	8.933ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	35.263m	8.777ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	35.327m	8.628ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.154m	9.123ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	29.600m	6.776ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	33.497m	9.022ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	38.579m	8.850ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	37.084m	8.313ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	40.105m	8.348ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	41.415m	10.159ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	46.944m	11.965ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	50.680m	12.012ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	51.018m	12.240ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	52.966m	11.646ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	41.727m	10.240ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	54.309m	12.074ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	51.596m	12.065ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	50.659m	11.595ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	50.722m	11.153ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.247m	7.637ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	30.786m	8.402ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	34.906m	8.518ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	36.265m	8.400ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	33.542m	8.487ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.905m	7.240ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	31.054m	9.100ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	31.248m	8.675ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	35.273m	8.765ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	35.763m	8.193ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	26.692m	6.555ms	3	3	100.00
		rom_e2e_asm_init_dev	36.107m	8.260ms	3	3	100.00
		rom_e2e_asm_init_prod	35.776m	9.032ms	3	3	100.00
		rom_e2e_asm_init_prod_end	40.870m	9.092ms	3	3	100.00
		rom_e2e_asm_init_rma	33.897m	9.008ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.358m	10.903ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.561m	3.047ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.483m	3.269ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.550m	3.307ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.876m	2.338ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.051m	4.980ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.184m	19.028ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.184m	19.028ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.513m	4.264ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.366m	4.268ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.513m	4.264ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.320m	10.124ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.320m	10.124ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.397m	6.450ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.699m	5.554ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.293m	6.570ms	3	3	100.00
		chip_sw_aes_idle	4.876m	2.338ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.508m	3.024ms	3	3	100.00
		chip_sw_kmac_idle	4.954m	3.368ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.340m	5.574ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.496m	4.564ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.531m	5.064ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.163m	4.872ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	26.107m	10.594ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.446m	4.381ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.039m	4.639ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.001m	3.785ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.001m	4.684ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.905m	4.384ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.696m	5.036ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.334m	7.902ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.108m	9.772ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.001m	3.785ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.001m	4.684ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	15.604m	5.562ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.088m	6.329ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.049h	18.905ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.483m	3.269ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.923m	5.887ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.732m	3.139ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.266m	3.934ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.698m	3.281ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.563m	5.653ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.378m	3.061ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.275m	2.718ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	15.245m	6.111ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.453m	7.265ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.071h	24.622ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.892m	3.339ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.241m	3.141ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	7.784m	4.665ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.498m	3.108ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.063m	4.721ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.688m	25.511ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	58.773m	18.727ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.334m	7.902ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.351m	4.924ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.138m	3.458ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.883m	6.594ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	34.992m	8.190ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	28.165m	8.691ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.508m	4.100ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	11.846m	6.059ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.364m	2.880ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	54.073m	12.662ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.199m	2.908ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.334m	5.236ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.199m	2.908ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	28.165m	8.691ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test	12.025m	4.856ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.747m	2.899ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	39.511m	21.099ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.368m	5.547ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.088m	6.329ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	15.267m	4.448ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	15.604m	5.562ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	39.511m	21.099ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.404m	3.125ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.656m	4.215ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.893m	5.003ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.893m	5.003ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.893m	5.003ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.893m	5.003ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.893m	5.003ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.883m	6.594ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.215m	5.753ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	10.086m	4.676ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.969m	3.458ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.732m	3.139ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.508m	3.024ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.941m	5.919ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	19.538m	5.811ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	17.211m	5.652ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.447m	4.212ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.656m	4.215ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.266m	3.934ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.433m	4.127ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.051m	4.980ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.306h	16.807ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.573m	2.803ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.337m	3.288ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.698m	3.281ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.656m	4.215ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.171m	2.529ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.230m	3.088ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.954m	3.368ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.786m	5.379ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	13.075m	7.506ms	5	5	100.00
		chip_tap_straps_rma	18.642m	8.669ms	5	5	100.00
		chip_tap_straps_prod	28.399m	14.051ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	5.230m	3.122ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.094m	4.530ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.893m	5.003ms	3	3	100.00
		chip_sw_flash_rma_unlocked			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.568m	3.602ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.796m	7.584ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.842m	8.820ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.167m	7.040ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.656m	4.215ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	12.569m	8.966ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.375m	9.348ms	3	3	100.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.108m	9.772ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.446m	4.381ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.039m	4.639ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.001m	3.785ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.001m	4.684ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.905m	4.384ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.696m	5.036ms	3	3	100.00
		chip_tap_straps_dev	13.075m	7.506ms	5	5	100.00
		chip_tap_straps_rma	18.642m	8.669ms	5	5	100.00
		chip_tap_straps_prod	28.399m	14.051ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.051m	3.092ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.139m	3.397ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.486m	2.653ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.619m	3.573ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	44.503m	31.832ms	3	3	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.574h	49.444ms	1	3	33.33
		chip_sw_lc_walkthrough_prod	1.423h	48.176ms	1	3	33.33
		chip_sw_lc_walkthrough_prodend	15.195m	8.574ms	3	3	100.00
		chip_sw_lc_walkthrough_rma			0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	44.503m	31.832ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	5.660m	3.724ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	5.190m	4.621ms	3	3	100.00
		rom_volatile_raw_unlock	32.562m	9.367ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	39.511m	21.099ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.237m	3.966ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.656m	4.215ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.919m	4.941ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.561m	3.597ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	39.511m	21.099ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.237m	3.966ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.656m	4.215ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.919m	4.941ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.561m	3.597ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.688m	5.866ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	5.230m	3.122ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.568m	3.602ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.796m	7.584ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.842m	8.820ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.167m	7.040ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.309m	14.407ms	15	15	100.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.185m	8.558ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	9.875m	8.645ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.319m	6.460ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	12.336m	9.720ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	11.752m	17.616ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.335m	9.601ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	22.189m	13.071ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.320m	10.124ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	22.675m	12.433ms	2	3	66.67
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.726m	4.192ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.185m	8.558ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.610m	4.774ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	58.527m	29.702ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.119m	7.929ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.168m	5.068ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	50.098m	28.360ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	16.524m	7.662ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	28.274m	10.283ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	42.607m	23.450ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	6.173m	3.402ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.883m	6.594ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.569m	8.966ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.569m	8.966ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	28.274m	10.283ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	50.098m	28.360ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	10.726m	4.192ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.366m	4.268ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.030m	3.880ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.352m	7.513ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.229m	4.905ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	32.536m	14.865ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.083m	2.947ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.883m	6.594ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	32.103m	8.432ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.034m	6.615ms	3	3	100.00
		chip_plic_all_irqs_10	11.420m	4.584ms	3	3	100.00
		chip_plic_all_irqs_20	15.202m	4.470ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.181m	2.277ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.362m	3.124ms	3	3	100.00
V2	chip_sw_spi_device_tx_rx	chip_sw_spi_device_tx_rx	7.516m	3.427ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	3.663h	73.771ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.698m	6.696ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	12.357m	4.760ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	8.654m	3.205ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.565m	3.246ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.919m	4.941ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.563m	5.653ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	15.857m	6.796ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	11.481m	6.802ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.375m	9.348ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.883m	6.594ms	99	100	99.00
		chip_sw_data_integrity_escalation	13.624m	6.333ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.200m	2.416ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.833m	3.221ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	0	--
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.450m	4.074ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	0	--
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.960h	31.652ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	55.375m	12.419ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	7.531m	3.604ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.786m	5.379ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.883m	6.594ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.672m	3.277ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	32.536m	14.865ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.954m	5.604ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.639m	3.891ms	87	90	96.67
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	20.630m	8.961ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	34.992m	8.190ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	32.103m	8.432ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.657h	254.460ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	35.401m	19.682ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	23.817m	13.094ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.030m	3.880ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	8.000m	3.842ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.289m	6.275ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	18.642m	8.669ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			840	2661	31.57
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.091m	3.590ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.763h	49.817ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.879m	5.121ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.486m	2.668ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.565m	2.140ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.891m	2.109ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.266h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.314h	51.069ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.121h	60.000ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	40.062m	10.231ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.206m	3.176ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_combo_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	16.524m	7.662ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	35.566m	25.151ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input	chip_sw_sysrst_ctrl_inputs	6.461m	3.434ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input_interrupt	chip_sw_sysrst_ctrl_in_irq	10.330m	4.007ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_ulp_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.539m	5.037ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.648m	3.288ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	28.617m	6.233ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	22.937m	6.264ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	10.572m	3.505ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_memory_protection			0	0	--
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.127m	2.152ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.850m	13.266ms	0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.814m	13.664ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	7.429m	4.421ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	28.274m	10.283ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.883m	6.594ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_watermarks			0	0	--
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.254h	19.386ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.486m	2.668ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.565m	2.140ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.891m	2.109ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.720m	5.985ms	3	3	100.00
V3		TOTAL			26	45	57.78
	Unmapped tests	chip_sival_flash_info_access	7.635m	3.385ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	10.341m	5.469ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	59.677m	17.052ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.429m	5.856ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.494m	5.262ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.894m	2.707ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.800m	2.589ms	3	3	100.00
		TOTAL			958	2953	32.44

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	7	7	7	100.00
V1	19	19	13	68.42
V2	290	276	230	79.31
V2S	1	1	1	100.00
V3	92	21	10	10.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.05	93.42	83.46	92.44	--	94.37	97.74	84.86

Failure Buckets

• launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:

  • Test chip_csr_bit_bash has 3 failures.

    • 0.chip_csr_bit_bash.33815018808062100434315613332359348183619219699854027063063177848245753681970
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

    • 2.chip_csr_bit_bash.38700208530650540276600252949577157882733068526726064232408889576075218095585
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log

    • ... and 1 more failures.

  • Test chip_same_csr_outstanding has 3 failures.

    • 0.chip_same_csr_outstanding.58203751972511739005606192533062551045810098029716739109407875732296959856993
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

    • 2.chip_same_csr_outstanding.7012083860316450500683120581920961031629871898223773063479910492740922217978
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log

    • ... and 1 more failures.

  • Test chip_prim_tl_access has 2 failures.

    • 0.chip_prim_tl_access.46547922435850973413394594194301002007519442598560367031569374156758140640312
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log

    • 2.chip_prim_tl_access.82106200665715771039573105456731923340968220989020131016057873247193434489015
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log

  • Test xbar_smoke has 8 failures.

    • 0.xbar_smoke.6515644774914498862346088212652424847061617907684782032277050275944535952801
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log

    • 2.xbar_smoke.64821815672927707787163823467433909889242451971054737559059534618565928454961
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log

    • ... and 6 more failures.

  • Test xbar_smoke_large_delays has 8 failures.

    • 0.xbar_smoke_large_delays.45644808733242483881514627657333676209589370336154020483595045320893212727314
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log

    • 2.xbar_smoke_large_delays.16049068611245638106398259806191072648496804274232071815619475558807415433318
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log

    • ... and 6 more failures.

  • ... and 22 more tests.

• Job killed most likely because its dependent job failed. has 955 failures:

  • Test chip_csr_aliasing has 3 failures.

    • 0.chip_csr_aliasing.85436124848377520378901269063976999951807423837105545180988787439160719065175
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

    • 2.chip_csr_aliasing.69574167507918962391960230511227956852128410479442670707091959516225268274175
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log

    • ... and 1 more failures.

  • Test chip_tl_errors has 8 failures.

    • 0.chip_tl_errors.45286628001331642462458307558100806270742247284697716625587012245522466742882
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

    • 2.chip_tl_errors.102709747961764374852116784644624098144442655492093149077180766861838687041695
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log

    • ... and 6 more failures.

  • Test chip_rv_dm_lc_disabled has 2 failures.

    • 0.chip_rv_dm_lc_disabled.53726681644596501543931796717876832826079644529820140723316308424124740666368
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

    • 2.chip_rv_dm_lc_disabled.6976155458893600081963215799085713645085381455308164257852952311984922855809
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log

  • Test xbar_smoke_zero_delays has 8 failures.

    • 0.xbar_smoke_zero_delays.113622152902920715241238492082477080218141687294940453114518296349563994597264
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log

    • 2.xbar_smoke_zero_delays.16330600929942254783019573443266869990033794870303990584229336907588659151352
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log

    • ... and 6 more failures.

  • Test xbar_smoke_slow_rsp has 8 failures.

    • 0.xbar_smoke_slow_rsp.17851439361758932135232837795930440259476016379900523788669850678465981029016
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log

    • 2.xbar_smoke_slow_rsp.36477707801724948524673008115357109754807167058674706055746310232972256470662
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log

    • ... and 6 more failures.

  • ... and 22 more tests.

• Exit reason: Error: User command failed Job returned non-zero exit code has 39 failures:

  • Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_meas.24631490181434671298911450912011055727216005437710219135569257799700221307336
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (15:22:36) Loading:
        (15:22:37) Loading:
        (15:22:37) Loading: 4 packages loaded
        (15:22:37) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:22:37) WARNING: Target pattern parsing failed.
        (15:22:37) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:22:37) INFO: Elapsed time: 18.125s
        (15:22:37) INFO: 0 processes.
        (15:22:37) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_meas.106300184848367642186061018909821000222258690075774522037290755057607353071826
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (15:32:41) Loading:
        (15:32:42) Loading:
        (15:32:42) Loading: 4 packages loaded
        (15:32:42) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:32:42) WARNING: Target pattern parsing failed.
        (15:32:42) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:32:42) INFO: Elapsed time: 18.809s
        (15:32:42) INFO: 0 processes.
        (15:32:42) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_no_meas.25365403556417767806893797840814923125533601390721033415827609096524521734837
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (15:22:59) Loading:
        (15:22:59) Loading:
        (15:22:59) Loading: 4 packages loaded
        (15:23:00) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:23:00) WARNING: Target pattern parsing failed.
        (15:23:00) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:23:00) INFO: Elapsed time: 23.129s
        (15:23:00) INFO: 0 processes.
        (15:23:00) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_no_meas.73586643323404442376931408828223231876932552706179308759977358816032982294551
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (15:33:36) Loading:
        (15:33:37) Loading:
        (15:33:38) Loading: 4 packages loaded
        (15:33:38) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:33:38) WARNING: Target pattern parsing failed.
        (15:33:38) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:33:38) INFO: Elapsed time: 28.102s
        (15:33:38) INFO: 0 processes.
        (15:33:38) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.81266907935106231089112668530079852558948329511413464136228469715818706549051
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (15:22:54) Loading:
        (15:22:55) Loading:
        (15:22:55) Loading: 4 packages loaded
        (15:22:55) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:22:55) WARNING: Target pattern parsing failed.
        (15:22:55) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:22:55) INFO: Elapsed time: 17.992s
        (15:22:55) INFO: 0 processes.
        (15:22:55) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.61080940188055403023537523404782346840481437544263215554344676450252219773543
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (15:33:06) Loading:
        (15:33:06) Loading:
        (15:33:06) Loading: 4 packages loaded
        (15:33:06) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:33:06) WARNING: Target pattern parsing failed.
        (15:33:06) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:33:06) INFO: Elapsed time: 18.071s
        (15:33:06) INFO: 0 processes.
        (15:33:06) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

    • 0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.115541319001777897225930813591416339327412402878436089825731296369690320912400
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (15:22:51) Loading:
        (15:22:52) Loading:
        (15:22:52) Loading: 4 packages loaded
        (15:22:52) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:22:52) WARNING: Target pattern parsing failed.
        (15:22:52) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:22:52) INFO: Elapsed time: 17.869s
        (15:22:52) INFO: 0 processes.
        (15:22:52) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.69343811678292483340563024526704796311858466448941805300230482387396753411846
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (15:33:14) Loading:
        (15:33:14) Loading:
        (15:33:14) Loading: 4 packages loaded
        (15:33:14) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:33:14) WARNING: Target pattern parsing failed.
        (15:33:14) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:33:14) INFO: Elapsed time: 25.051s
        (15:33:14) INFO: 0 processes.
        (15:33:14) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_sigverify_mod_exp_test_unlocked0_sw has 3 failures.

    • 0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.94006726472759669408866068522818932976350148657046074379750399685605145400101
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

        (15:22:59) Loading:
        (15:22:59) Loading:
        (15:22:59) Loading: 4 packages loaded
        (15:23:00) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:23:00) WARNING: Target pattern parsing failed.
        (15:23:00) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:23:00) INFO: Elapsed time: 17.294s
        (15:23:00) INFO: 0 processes.
        (15:23:00) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.61616336393921464518331600018598760069780146989104794830986310974854223226051
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

        (15:33:08) Loading:
        (15:33:08) Loading:
        (15:33:08) Loading: 4 packages loaded
        (15:33:09) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:33:09) WARNING: Target pattern parsing failed.
        (15:33:09) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:33:09) INFO: Elapsed time: 19.600s
        (15:33:09) INFO: 0 processes.
        (15:33:09) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • ... and 8 more tests.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:

  • Test chip_sw_flash_rma_unlocked has 3 failures.

    • 0.chip_sw_flash_rma_unlocked.12935733996220871522928041007389061002975861622543197194508918997890802692002
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log

        Job ID: smart:e41c2a58-b555-4599-97a9-93484f556e00
      

    • 1.chip_sw_flash_rma_unlocked.106736107526920884071023249016206891872372750266662345977826544533841584047839
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log

        Job ID: smart:a7f7c668-3c95-4579-9c84-c96776cf5149
      

    • ... and 1 more failures.

  • Test chip_sw_lc_walkthrough_prod has 2 failures.

    • 0.chip_sw_lc_walkthrough_prod.48962602595138394860771488175428865031608428331533185238853803894322858288094
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

        Job ID: smart:8a175f63-fcca-4a32-b80b-fadce3dcca2e
      

    • 2.chip_sw_lc_walkthrough_prod.98454531440220429384324306353981405144220441143812698475894640124181387554027
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log

        Job ID: smart:8a32a7bb-4434-41c9-87b2-10799df4ba4a
      

  • Test chip_sw_lc_walkthrough_rma has 3 failures.

    • 0.chip_sw_lc_walkthrough_rma.65319592031973483112021354090262744428417678389871585060270840448898393948616
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

        Job ID: smart:b138d437-0e2c-41f1-86c6-f74b258a57fa
      

    • 1.chip_sw_lc_walkthrough_rma.78348262541844549048045026920778929647163816179767809725170033126392960378797
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

        Job ID: smart:affd9dbc-8762-4b2e-ba20-2f36b1fa8251
      

    • ... and 1 more failures.

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.61780683118839513718696687012439029487551489427594926605933444447650738484923
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:7bea7da1-03d3-4833-8e81-7db15632b885
      

    • 1.chip_sw_rv_timer_systick_test.74877922715237280582296271539775189137611975858985082183878270790649860933389
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:daacb027-86d0-420e-915c-2a3beeb02cc2
      

    • ... and 1 more failures.

  • Test chip_sw_lc_walkthrough_dev has 2 failures.

    • 1.chip_sw_lc_walkthrough_dev.10946433922433079234115761125557723834811325237273473866362111003893728791162
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

        Job ID: smart:44d1b851-2b03-491b-af07-00c51a2054da
      

    • 2.chip_sw_lc_walkthrough_dev.16630851920552401453102997627587869938343822395755166085303592199844053014693
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log

        Job ID: smart:0dd4d1ab-d47c-4784-803a-60661ce92d3b
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:

  • Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 3 failures.

    • 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.37803498333210556737978057140588736720775354765371031441839244582817026285583
      Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 6460.275580 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 6460.275580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2800053766758593754908822233268490623435097510703005258546175647147493047388
      Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 6527.929532 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 6527.929532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:

  • Test chip_sw_pwrmgr_deep_sleep_all_wake_ups has 3 failures.

    • 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.32815388562711273666842978686578195091628963415517291892208252616153161301203
      Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 11723.600280 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 11723.600280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.14843962181809865708855482345280272514469057477516857550029596152033378332213
      Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 9601.049586 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 9601.049586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:

  • Test chip_sw_pwrmgr_random_sleep_all_wake_ups has 3 failures.

    • 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1464211007939999800842757990091188607764454431162998723024364653526988403223
      Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 8913.145416 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 8913.145416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.53095596566980871956628050963647245071168620833369324945741758681165141372497
      Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log

        UVM_ERROR @ 8354.775440 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
        UVM_INFO @ 8354.775440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep has 3 failures:

  • Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.

    • 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.100479692458919474887978802818075505186906497712762312152760007342658414521311
      Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 12926.601464 us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep
        UVM_INFO @ 12926.601464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.102461042060528557686698485381120234296691583385463866572207804951299782598188
      Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log

        UVM_FATAL @ 13042.168116 us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep
        UVM_INFO @ 13042.168116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 3 failures:

  • Test chip_sw_power_virus has 3 failures.

    • 0.chip_sw_power_virus.24151858087303757107916008429790335545760402522774652759911735116189402462125
      Line 941, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 5120.797059 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 5120.797059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_power_virus.89619864227726953238735449077129671149916604880259100051654114079812111488232
      Line 957, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 4842.916442 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 4842.916442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.71494921901976459424676812724087817985902989754186772387599255249112140152554
      Line 723, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 2667.870500 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2667.870500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.47090520185537415440928597516450371243085955652590618599184778816863187849974
      Line 709, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2140.023500 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2140.023500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.10390087049662214308962294722955980743820626931253060599163620483107677431332
      Line 706, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 2109.138500 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2109.138500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

  • Test rom_e2e_self_hash has 3 failures.

    • 0.rom_e2e_self_hash.74429606066649508504842654642068454456387583599150201838794540305891604116850
      Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 10231.316762 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
        UVM_INFO @ 10231.316762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_e2e_self_hash.61094551937892201331158586086328172793113353770989190282513091915263191811583
      Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 9419.430124 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
        UVM_INFO @ 9419.430124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 3 failures.

    • 28.chip_sw_alert_handler_lpg_sleep_mode_alerts.19981087483455749963195312482021455030616497951052330496020539001245928578355
      Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3897.358500 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
        UVM_INFO @ 3897.358500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.chip_sw_alert_handler_lpg_sleep_mode_alerts.99813133569751067080201164844822091072694915817045809308128677425929648275208
      Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3066.887852 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
        UVM_INFO @ 3066.887852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 2 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.13361767149021998274825201897915750915754512723166821380909810561216566703413
      Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
        UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.101658217879942257902478618607944037482056679669629686531273872326939262686029
      Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
        UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:

  • Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.

    • 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.94628175899602351218882468950771860341147728646038500710632991019004458308597
      Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log

            Offending '(pend_req[h2d.a_source].pend == 0)'
        UVM_ERROR @ 7136.512908 us: (tlul_assert.sv:263) [ASSERT FAILED] pendingReqPerSrc_M
        UVM_INFO @ 7136.512908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.

    • 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.96726191589293077970417992846299967612840400868431079319117159224317287868294
      Line 833, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log

            Offending '(pend_req[h2d.a_source].pend == 0)'
        UVM_ERROR @ 20256.619560 us: (tlul_assert.sv:263) [ASSERT FAILED] pendingReqPerSrc_M
        UVM_INFO @ 20256.619560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done. has 1 failures:

  • Test chip_sw_otp_ctrl_escalation has 1 failures.

    • 0.chip_sw_otp_ctrl_escalation.23651172247944859654141810529771685354022895723499808299919359454117343012691
      Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log

        UVM_FATAL @ 13266.023950 us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done.
        UVM_INFO @ 13266.023950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.44782277778388402062793257275344702997795906091887684319480017803282358803438
      Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 51069.384005 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 51069.384005 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:

  • Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.

    • 2.chip_sw_pwrmgr_normal_sleep_por_reset.80944543615872575398958060569463892614665016010147043037768050143999901206570
      Line 749, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

        UVM_ERROR @ 17616.491839 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 17616.491839 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:

  • Test chip_sw_all_escalation_resets has 1 failures.

    • 80.chip_sw_all_escalation_resets.43896370778625398705894115826706007763456152460381026340064061591812413035806
      Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2921.603036 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2921.603036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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