Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
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Group : chip_env_pkg::chip_alert_cg_wrap::alert_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_chip_env_0.1/chip_env_cov.sv

65 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
adc_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
aes_fatal_fault 100.00 1 100 1 64 64
aes_recov_ctrl_update_err 100.00 1 100 1 64 64
aon_timer_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_fatal_fault 100.00 1 100 1 64 64
clkmgr_aon_recov_fault 100.00 1 100 1 64 64
csrng_fatal_alert 100.00 1 100 1 64 64
csrng_recov_alert 100.00 1 100 1 64 64
edn0_fatal_alert 100.00 1 100 1 64 64
edn0_recov_alert 100.00 1 100 1 64 64
edn1_fatal_alert 100.00 1 100 1 64 64
edn1_recov_alert 100.00 1 100 1 64 64
entropy_src_fatal_alert 100.00 1 100 1 64 64
entropy_src_recov_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_err 100.00 1 100 1 64 64
flash_ctrl_fatal_prim_flash_alert 100.00 1 100 1 64 64
flash_ctrl_fatal_std_err 100.00 1 100 1 64 64
flash_ctrl_recov_err 100.00 1 100 1 64 64
flash_ctrl_recov_prim_flash_alert 100.00 1 100 1 64 64
gpio_fatal_fault 100.00 1 100 1 64 64
hmac_fatal_fault 100.00 1 100 1 64 64
i2c0_fatal_fault 100.00 1 100 1 64 64
i2c1_fatal_fault 100.00 1 100 1 64 64
i2c2_fatal_fault 100.00 1 100 1 64 64
keymgr_fatal_fault_err 100.00 1 100 1 64 64
keymgr_recov_operation_err 100.00 1 100 1 64 64
kmac_fatal_fault_err 100.00 1 100 1 64 64
kmac_recov_operation_err 100.00 1 100 1 64 64
lc_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
lc_ctrl_fatal_prog_error 100.00 1 100 1 64 64
lc_ctrl_fatal_state_error 100.00 1 100 1 64 64
otbn_fatal 100.00 1 100 1 64 64
otbn_recov 100.00 1 100 1 64 64
otp_ctrl_fatal_bus_integ_error 100.00 1 100 1 64 64
otp_ctrl_fatal_check_error 100.00 1 100 1 64 64
otp_ctrl_fatal_macro_error 100.00 1 100 1 64 64
otp_ctrl_fatal_prim_otp_alert 100.00 1 100 1 64 64
otp_ctrl_recov_prim_otp_alert 100.00 1 100 1 64 64
pattgen_fatal_fault 100.00 1 100 1 64 64
pinmux_aon_fatal_fault 100.00 1 100 1 64 64
pwm_aon_fatal_fault 100.00 1 100 1 64 64
pwrmgr_aon_fatal_fault 100.00 1 100 1 64 64
rom_ctrl_fatal 100.00 1 100 1 64 64
rstmgr_aon_fatal_cnsty_fault 100.00 1 100 1 64 64
rstmgr_aon_fatal_fault 100.00 1 100 1 64 64
rv_core_ibex_fatal_hw_err 100.00 1 100 1 64 64
rv_core_ibex_fatal_sw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_hw_err 100.00 1 100 1 64 64
rv_core_ibex_recov_sw_err 100.00 1 100 1 64 64
rv_dm_fatal_fault 100.00 1 100 1 64 64
rv_plic_fatal_fault 100.00 1 100 1 64 64
rv_timer_fatal_fault 100.00 1 100 1 64 64
sensor_ctrl_aon_fatal_alert 100.00 1 100 1 64 64
sensor_ctrl_aon_recov_alert 100.00 1 100 1 64 64
spi_device_fatal_fault 100.00 1 100 1 64 64
spi_host0_fatal_fault 100.00 1 100 1 64 64
spi_host1_fatal_fault 100.00 1 100 1 64 64
sram_ctrl_main_fatal_error 100.00 1 100 1 64 64
sram_ctrl_ret_aon_fatal_error 100.00 1 100 1 64 64
sysrst_ctrl_aon_fatal_fault 100.00 1 100 1 64 64
uart0_fatal_fault 100.00 1 100 1 64 64
uart1_fatal_fault 100.00 1 100 1 64 64
uart2_fatal_fault 100.00 1 100 1 64 64
uart3_fatal_fault 100.00 1 100 1 64 64
usbdev_fatal_fault 100.00 1 100 1 64 64




Group Instance : adc_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance adc_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance adc_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aes_recov_ctrl_update_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aes_recov_ctrl_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aes_recov_ctrl_update_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : aon_timer_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance aon_timer_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance aon_timer_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : clkmgr_aon_recov_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance clkmgr_aon_recov_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance clkmgr_aon_recov_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : csrng_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance csrng_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance csrng_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn0_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn0_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn0_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : edn1_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn1_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance edn1_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : entropy_src_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance entropy_src_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance entropy_src_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_fatal_std_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_fatal_std_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_fatal_std_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : flash_ctrl_recov_prim_flash_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_recov_prim_flash_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance flash_ctrl_recov_prim_flash_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : gpio_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance gpio_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance gpio_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : hmac_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance hmac_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance hmac_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : i2c2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance i2c2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance i2c2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : keymgr_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance keymgr_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance keymgr_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_fatal_fault_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_fatal_fault_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_fatal_fault_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : kmac_recov_operation_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance kmac_recov_operation_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance kmac_recov_operation_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_prog_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_prog_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_prog_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : lc_ctrl_fatal_state_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lc_ctrl_fatal_state_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance lc_ctrl_fatal_state_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otbn_recov
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otbn_recov

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otbn_recov
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_bus_integ_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_bus_integ_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_bus_integ_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_check_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_check_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_check_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_macro_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_macro_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_macro_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_fatal_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_fatal_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_fatal_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : otp_ctrl_recov_prim_otp_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance otp_ctrl_recov_prim_otp_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance otp_ctrl_recov_prim_otp_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pattgen_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pattgen_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pattgen_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pinmux_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pinmux_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pinmux_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwm_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwm_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwm_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : pwrmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance pwrmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance pwrmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rom_ctrl_fatal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rom_ctrl_fatal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rom_ctrl_fatal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_cnsty_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_cnsty_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_cnsty_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rstmgr_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rstmgr_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rstmgr_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_fatal_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_fatal_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_fatal_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_hw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_hw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_hw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_core_ibex_recov_sw_err
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_core_ibex_recov_sw_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_core_ibex_recov_sw_err
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_dm_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_dm_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_dm_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_plic_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_plic_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_plic_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : rv_timer_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance rv_timer_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance rv_timer_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_fatal_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_fatal_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_fatal_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sensor_ctrl_aon_recov_alert
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sensor_ctrl_aon_recov_alert

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sensor_ctrl_aon_recov_alert
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_device_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_device_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_device_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : spi_host1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance spi_host1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance spi_host1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_main_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_main_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_main_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sram_ctrl_ret_aon_fatal_error
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sram_ctrl_ret_aon_fatal_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sram_ctrl_ret_aon_fatal_error
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : sysrst_ctrl_aon_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_aon_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance sysrst_ctrl_aon_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart0_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart0_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart0_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart1_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart1_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart1_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart2_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart2_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart2_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : uart3_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance uart3_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance uart3_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2



Group Instance : usbdev_fatal_fault
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance usbdev_fatal_fault

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 1 0 1 100.00


Variables for Group Instance usbdev_fatal_fault
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
triggered_cp 1 0 1 100.00 100 1 1 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4763 1 T38 810 T56 25 T211 819


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 111941 1 T28 1 T20 1441 T36 34


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 169 1 T28 1 T56 27 T110 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2829 1 T56 17 T110 1 T602 515


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4363 1 T595 812 T56 27 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 774 1 T56 21 T601 101 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2469 1 T56 26 T22 1 T8 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 154 1 T28 1 T56 25 T110 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3610 1 T56 31 T587 1722 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 147 1 T56 24 T585 1 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4748 1 T28 1 T56 29 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 149 1 T28 1 T56 36 T206 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6363 1 T28 1 T56 31 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 153 1 T28 2 T56 27 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8810 1 T28 1 T18 498 T78 483


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4106 1 T56 18 T228 1142 T132 1714


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3578 1 T56 25 T22 1 T57 40


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 246 1 T28 1 T18 3 T78 3


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 134 1 T56 25 T22 1 T57 35


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 986 1 T28 1 T56 24 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5955 1 T28 1 T56 25 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3649 1 T56 30 T205 813 T597 516


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4998 1 T56 36 T598 527 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4969 1 T56 32 T599 515 T600 811


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7588 1 T56 27 T22 1 T57 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 171 1 T28 1 T18 1 T86 2


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 116527 1 T28 1 T20 1441 T36 34


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 154 1 T56 27 T22 1 T57 43


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4988 1 T56 36 T139 521 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1860 1 T28 1 T37 566 T56 26


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1797 1 T56 33 T22 1 T213 812


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 109936 1 T20 1441 T36 34 T38 586


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 164 1 T56 29 T100 1 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2526 1 T56 32 T22 1 T57 46


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 51402 1 T28 1 T20 678 T36 16


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 156 1 T56 19 T22 1 T57 34


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3444 1 T56 31 T22 1 T57 40


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 154 1 T28 1 T56 30 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2841 1 T28 1 T201 816 T56 27


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4188 1 T39 813 T55 528 T56 41


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3555 1 T28 1 T56 21 T669 514


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8557 1 T28 1 T20 1 T56 23


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8696 1 T72 1116 T56 28 T214 1726


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2585 1 T28 1 T56 14 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1522 1 T28 1 T56 24 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 38387 1 T28 1 T91 343 T74 311


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 6918 1 T28 501 T56 34 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 112 1 T28 1 T56 11 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 235 1 T28 1 T44 1 T56 29


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8220 1 T131 1157 T56 27 T8 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 5352 1 T28 1 T56 38 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3363 1 T56 34 T269 530 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4721 1 T28 62 T56 23 T110 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 10956 1 T28 62 T56 25 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2300 1 T28 1 T117 813 T56 23


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 8016 1 T56 23 T22 1 T319 1683


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 7896 1 T28 1 T56 35 T110 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1879 1 T56 31 T110 1 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 176 1 T28 1 T56 23 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3103 1 T56 30 T22 1 T57 34


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2032 1 T28 1 T56 20 T22 1


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4698 1 T28 1 T294 517 T56 38


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 2560 1 T28 1 T56 34 T233 518


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 3631 1 T56 24 T272 814 T596 519


Summary for Variable triggered_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 1 0 1 100.00


Automatically Generated Bins for triggered_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
ignore 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 4056 1 T56 28 T110 1 T133 1293

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%