Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2627988 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 27384096 1 T28 2549 T29 192 T30 204


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 19709811 1 T28 2330 T29 52 T30 29
values[0x0] 8417405 1 T28 1198 T29 107 T30 86
values[0x1] 1884868 1 T28 1210 T29 1032 T30 89


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 777023 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 29235061 1 T28 3079 T29 885 T30 204


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 13694868 1 T28 70 T29 10 T30 3
valid_sources[0x01] 13694595 1 T28 78 T29 35 T30 8
valid_sources[0x02] 42636 1 T28 74 T29 6 T30 5
valid_sources[0x03] 46061 1 T28 78 T29 20 T30 5
valid_sources[0x04] 42167 1 T28 87 T29 10 T122 83
valid_sources[0x05] 42992 1 T28 80 T29 9 T30 5
valid_sources[0x06] 42384 1 T28 74 T29 14 T122 39
valid_sources[0x07] 41546 1 T28 47 T29 20 T30 2
valid_sources[0x08] 42192 1 T28 59 T29 11 T30 2
valid_sources[0x09] 41717 1 T28 64 T29 22 T30 9
valid_sources[0x0a] 42195 1 T28 73 T29 18 T30 4
valid_sources[0x0b] 41895 1 T28 64 T29 13 T30 2
valid_sources[0x0c] 42334 1 T28 82 T29 35 T30 5
valid_sources[0x0d] 41942 1 T28 64 T29 12 T30 3
valid_sources[0x0e] 42273 1 T28 66 T29 10 T30 3
valid_sources[0x0f] 42297 1 T28 93 T29 20 T30 1
valid_sources[0x10] 41911 1 T28 75 T29 23 T30 8
valid_sources[0x11] 44377 1 T28 73 T29 16 T30 2
valid_sources[0x12] 41243 1 T28 66 T29 12 T30 1
valid_sources[0x13] 42020 1 T28 68 T29 8 T30 10
valid_sources[0x14] 42486 1 T28 84 T29 11 T30 2
valid_sources[0x15] 41663 1 T28 83 T29 10 T30 4
valid_sources[0x16] 42214 1 T28 76 T29 21 T30 4
valid_sources[0x17] 42707 1 T28 51 T29 70 T122 153
valid_sources[0x18] 41725 1 T28 54 T29 29 T122 139
valid_sources[0x19] 41890 1 T28 81 T29 20 T30 2
valid_sources[0x1a] 42236 1 T28 63 T29 18 T30 7
valid_sources[0x1b] 41991 1 T28 78 T29 9 T122 86
valid_sources[0x1c] 41648 1 T28 67 T29 9 T122 42
valid_sources[0x1d] 42978 1 T28 76 T29 24 T30 1
valid_sources[0x1e] 42209 1 T28 74 T29 25 T30 7
valid_sources[0x1f] 42175 1 T28 74 T29 17 T30 4
valid_sources[0x20] 41414 1 T28 85 T29 16 T30 2


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 18788764 1 T28 1195 T29 47 T30 29
values[0x0] all_enables biggest_size 8376416 1 T28 741 T29 76 T30 86
values[0x1] all_enables biggest_size 218916 1 T28 613 T29 69 T30 89


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2834394 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 447393 1 T31 291 T32 363 T53 330


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1110571 1 T31 646 T32 865 T53 768
values[0x0] 1059087 1 T31 681 T32 838 T53 748
values[0x1] 1112129 1 T31 721 T32 837 T53 752


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2193292 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1088495 1 T31 695 T32 890 T53 753


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 51828 1 T31 47 T32 31 T53 41
valid_sources[0x01] 51944 1 T31 20 T32 31 T53 35
valid_sources[0x02] 51990 1 T31 25 T32 42 T53 27
valid_sources[0x03] 50772 1 T31 29 T32 30 T53 33
valid_sources[0x04] 48875 1 T31 31 T32 49 T53 40
valid_sources[0x05] 50282 1 T31 39 T32 46 T53 39
valid_sources[0x06] 50670 1 T31 33 T32 35 T53 40
valid_sources[0x07] 51743 1 T31 33 T32 34 T53 38
valid_sources[0x08] 50947 1 T31 34 T32 48 T53 37
valid_sources[0x09] 51781 1 T31 31 T32 49 T53 39
valid_sources[0x0a] 51410 1 T31 27 T32 47 T53 35
valid_sources[0x0b] 51261 1 T31 31 T32 36 T53 45
valid_sources[0x0c] 51785 1 T31 33 T32 33 T53 33
valid_sources[0x0d] 51663 1 T31 42 T32 32 T53 24
valid_sources[0x0e] 51565 1 T31 26 T32 26 T53 30
valid_sources[0x0f] 51066 1 T31 36 T32 49 T53 23
valid_sources[0x10] 50990 1 T31 46 T32 36 T53 27
valid_sources[0x11] 52163 1 T31 22 T32 50 T53 38
valid_sources[0x12] 50967 1 T31 25 T32 44 T53 29
valid_sources[0x13] 52188 1 T31 39 T32 47 T53 35
valid_sources[0x14] 51503 1 T31 37 T32 47 T53 29
valid_sources[0x15] 51568 1 T31 41 T32 45 T53 38
valid_sources[0x16] 51203 1 T31 25 T32 33 T53 41
valid_sources[0x17] 51813 1 T31 34 T32 34 T53 29
valid_sources[0x18] 51336 1 T31 30 T32 36 T53 40
valid_sources[0x19] 50265 1 T31 41 T32 41 T53 36
valid_sources[0x1a] 52394 1 T31 29 T32 28 T53 41
valid_sources[0x1b] 51728 1 T31 39 T32 49 T53 27
valid_sources[0x1c] 51747 1 T31 24 T32 45 T53 29
valid_sources[0x1d] 51435 1 T31 34 T32 48 T53 33
valid_sources[0x1e] 51259 1 T31 48 T32 40 T53 30
valid_sources[0x1f] 50289 1 T31 19 T32 34 T53 44
valid_sources[0x20] 52047 1 T31 38 T32 36 T53 30


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 46738 1 T31 26 T32 35 T53 30
values[0x0] all_enables biggest_size 353683 1 T31 237 T32 306 T53 260
values[0x1] all_enables biggest_size 46972 1 T31 28 T32 22 T53 40


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3025209 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 492181 1 T31 208 T32 403 T53 314


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1202459 1 T31 572 T32 1006 T53 794
values[0x0] 1110239 1 T31 519 T32 910 T53 730
values[0x1] 1204692 1 T31 595 T32 941 T53 782


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2322135 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1195255 1 T31 546 T32 1002 T53 760


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 54236 1 T31 3 T32 30 T53 32
valid_sources[0x01] 54183 1 T31 46 T32 20 T53 31
valid_sources[0x02] 56350 1 T31 31 T32 35 T53 31
valid_sources[0x03] 54946 1 T31 25 T32 48 T53 23
valid_sources[0x04] 54478 1 T31 14 T32 28 T53 34
valid_sources[0x05] 54480 1 T31 46 T32 32 T53 22
valid_sources[0x06] 55399 1 T31 27 T32 28 T53 40
valid_sources[0x07] 55334 1 T31 20 T32 41 T53 25
valid_sources[0x08] 55122 1 T31 30 T32 35 T53 33
valid_sources[0x09] 54418 1 T31 21 T32 31 T53 38
valid_sources[0x0a] 55015 1 T31 7 T32 39 T53 37
valid_sources[0x0b] 54710 1 T31 8 T32 40 T53 45
valid_sources[0x0c] 54730 1 T31 27 T32 46 T53 31
valid_sources[0x0d] 56766 1 T31 23 T32 73 T53 37
valid_sources[0x0e] 55329 1 T31 36 T32 58 T53 37
valid_sources[0x0f] 55293 1 T31 24 T32 56 T53 34
valid_sources[0x10] 54656 1 T31 19 T32 37 T53 26
valid_sources[0x11] 54800 1 T31 44 T32 49 T53 39
valid_sources[0x12] 54466 1 T31 17 T32 36 T53 29
valid_sources[0x13] 54719 1 T31 27 T32 19 T53 28
valid_sources[0x14] 55003 1 T31 66 T32 79 T53 29
valid_sources[0x15] 55496 1 T31 26 T32 66 T53 49
valid_sources[0x16] 55523 1 T31 52 T32 15 T53 32
valid_sources[0x17] 55672 1 T31 22 T32 21 T53 43
valid_sources[0x18] 55076 1 T31 56 T32 61 T53 41
valid_sources[0x19] 55044 1 T31 11 T32 22 T53 40
valid_sources[0x1a] 55374 1 T31 20 T32 99 T53 36
valid_sources[0x1b] 55518 1 T31 27 T32 54 T53 43
valid_sources[0x1c] 54532 1 T31 15 T32 51 T53 40
valid_sources[0x1d] 54742 1 T31 47 T32 54 T53 37
valid_sources[0x1e] 54900 1 T31 24 T32 27 T53 37
valid_sources[0x1f] 55423 1 T31 23 T32 33 T53 42
valid_sources[0x20] 55441 1 T31 30 T32 56 T53 49


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 51584 1 T31 19 T32 28 T53 43
values[0x0] all_enables biggest_size 389083 1 T31 168 T32 335 T53 239
values[0x1] all_enables biggest_size 51514 1 T31 21 T32 40 T53 32


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2862001 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 453322 1 T31 280 T32 372 T53 314


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 1123279 1 T31 736 T32 949 T53 692
values[0x0] 1069881 1 T31 691 T32 902 T53 690
values[0x1] 1122163 1 T31 663 T32 926 T53 705


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2216140 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1099183 1 T31 682 T32 875 T53 703


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 51520 1 T31 29 T32 32 T53 33
valid_sources[0x01] 51319 1 T31 27 T32 40 T53 32
valid_sources[0x02] 52669 1 T31 22 T32 38 T53 36
valid_sources[0x03] 51275 1 T31 22 T32 26 T53 34
valid_sources[0x04] 51068 1 T31 36 T32 28 T53 42
valid_sources[0x05] 51295 1 T31 40 T32 33 T53 28
valid_sources[0x06] 51782 1 T31 47 T32 35 T53 28
valid_sources[0x07] 52528 1 T31 40 T32 22 T53 44
valid_sources[0x08] 51709 1 T31 32 T32 61 T53 41
valid_sources[0x09] 52251 1 T31 24 T32 65 T53 37
valid_sources[0x0a] 51340 1 T31 33 T32 30 T53 33
valid_sources[0x0b] 51521 1 T31 35 T32 24 T53 34
valid_sources[0x0c] 52501 1 T31 58 T32 49 T53 30
valid_sources[0x0d] 52577 1 T31 37 T32 55 T53 33
valid_sources[0x0e] 52110 1 T31 40 T32 34 T53 37
valid_sources[0x0f] 52064 1 T31 36 T32 31 T53 31
valid_sources[0x10] 52405 1 T31 28 T32 30 T53 36
valid_sources[0x11] 52263 1 T31 37 T32 81 T53 27
valid_sources[0x12] 51515 1 T31 26 T32 31 T53 35
valid_sources[0x13] 51186 1 T31 48 T32 36 T53 36
valid_sources[0x14] 51819 1 T31 22 T32 63 T53 33
valid_sources[0x15] 51594 1 T31 53 T32 24 T53 33
valid_sources[0x16] 51662 1 T31 58 T32 38 T53 29
valid_sources[0x17] 52017 1 T31 27 T32 51 T53 32
valid_sources[0x18] 50908 1 T31 19 T32 42 T53 47
valid_sources[0x19] 52838 1 T31 39 T32 68 T53 31
valid_sources[0x1a] 52103 1 T31 34 T32 24 T53 23
valid_sources[0x1b] 51709 1 T31 27 T32 52 T53 30
valid_sources[0x1c] 52273 1 T31 44 T32 40 T53 36
valid_sources[0x1d] 51796 1 T31 41 T32 85 T53 24
valid_sources[0x1e] 52816 1 T31 12 T32 45 T53 23
valid_sources[0x1f] 50860 1 T31 46 T32 71 T53 32
valid_sources[0x20] 52339 1 T31 18 T32 26 T53 35


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 47944 1 T31 28 T32 37 T53 41
values[0x0] all_enables biggest_size 358186 1 T31 219 T32 300 T53 239
values[0x1] all_enables biggest_size 47192 1 T31 33 T32 35 T53 34

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%