Unified Coverage Report :: Module :: tlul_cmd_intg_chk

Module : tlul_cmd_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.17	100.00	76.67			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.98	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.68			100.00	100.00	u_reg_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

Line Coverage for Module : tlul_cmd_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Module : tlul_cmd_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	9554	9554	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	9554	9554	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	3	3	0	0
T31	3	3	0	0
T32	3	3	0	0
T53	3	3	0	0
T54	3	3	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T102	3	3	0	0
T221	3	3	0	0
T222	3	3	0	0
T223	3	3	0	0
T224	3	3	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	2866	2866	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	956	956	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	2866	2866	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	2866	2866	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0