Unified Coverage Report :: Module :: pinmux_strap_sampling

Module : pinmux_strap_sampling

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	99.34	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling	99.83	99.34	100.00			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	99.34	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.82	99.62	95.65			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.73	99.00	87.94	98.66		84.58	88.46	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pinmux_jtag_buf_dft	100.00	100.00
u_pinmux_jtag_buf_lc	100.00	100.00
u_pinmux_jtag_buf_rv	100.00	100.00
u_por_scanmode_sync	100.00						100.00
u_prim_lc_or_hardened	100.00	100.00	100.00				100.00
u_prim_lc_sender_pinmux_hw_debug_en	100.00	100.00				100.00
u_prim_lc_sync_lc_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_pinmux_hw_debug_en	100.00	100.00					100.00
u_rst_por_aon_n_mux	85.19	100.00	55.56				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pinmux_strap_sampling

	Line No.	Total	Covered	Percent
TOTAL		303	301	99.34
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	257	1	1	100.00
ALWAYS	260	9	9	100.00
ALWAYS	281	9	9	100.00
CONT_ASSIGN	306	1	1	100.00
ALWAYS	310	17	17	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
132	1	1
133	1	1
153	1	1
157	1	1
186	1	1
228	1	1
230	1	1
234	1	1
238	1	1
239	1	1
240	1	1
257	1	1
260	1	1
261	1	1
262	1	1
266	1	1
267	1	1
			MISSING_ELSE
272	1	1
273	1	1
274	1	1
275	1	1
			MISSING_ELSE
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
287	1	1
288	1	1
289	1	1
290	1	1
306	1	1
310	1	1
313	1	1
314	1	1
315	1	1
317	1	1
319	1	1
321	1	1
322	1	1
323	1	1
326	1	1
327	1	1
328	1	1
329	1	1
			MISSING_ELSE
333	1	1
334	1	1
335	1	1
336	1	1
			MISSING_ELSE
369	1	1
370	1	1
371	1	1
394	5	5
398	1	1
399	1	1
402	4	4
403	4	4
408	5	5
411	58	58
412	58	58
413	56	58
414	58	58

---

Cond Coverage for Module : pinmux_strap_sampling

	Total	Covered	Percent
Conditions	55	55	100.00
Logical	55	55	100.00
Non-Logical	0	0
Event	0	0

 LINE       228
 EXPRESSION (lc_strap_sample_en ? in_padring_i[30] : tap_strap_q[0])
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       230
 EXPRESSION (rv_strap_sample_en ? in_padring_i[27] : tap_strap_q[1])
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T18,T19

 LINE       234
 EXPRESSION (dft_strap_sample_en ? ({in_padring_i[26], in_padring_i[25]}) : dft_strap_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T19,T20

 LINE       238
 EXPRESSION (dft_strap_sample_en | dft_strap_valid_q)
             ---------1---------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T19,T20
1	0	Covered	T17,T19,T20

 LINE       266
 EXPRESSION (strap_en_q && tap_sampling_en)
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T19,T20

 LINE       272
 EXPRESSION (strap_en_q || tap_sampling_en)
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T19,T20
1	0	Covered	T1,T2,T3

 LINE       394
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       394
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       394
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       394
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       394
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       398
 EXPRESSION (jtag_en ? jtag_rsp.tdo : out_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       399
 EXPRESSION (jtag_en ? jtag_rsp.tdo_oe : oe_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       402
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       402
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       402
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       402
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       403
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       403
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       403
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       403
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       408
 EXPRESSION (jtag_en ? '0 : attr_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       408
 EXPRESSION (jtag_en ? '0 : attr_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       408
 EXPRESSION (jtag_en ? '0 : attr_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       408
 EXPRESSION (jtag_en ? '0 : attr_core_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

 LINE       408
 EXPRESSION (jtag_en ? '0 : attr_core_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T45,T36

---

Branch Coverage for Module : pinmux_strap_sampling

	Line No.	Total	Covered	Percent
Branches		59	59	100.00
TERNARY	228	2	2	100.00
TERNARY	230	2	2	100.00
TERNARY	234	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	402	2	2	100.00
TERNARY	403	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	398	2	2	100.00
TERNARY	399	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	402	2	2	100.00
TERNARY	403	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	402	2	2	100.00
TERNARY	403	2	2	100.00
TERNARY	394	2	2	100.00
TERNARY	408	2	2	100.00
TERNARY	402	2	2	100.00
TERNARY	403	2	2	100.00
IF	266	2	2	100.00
IF	272	3	3	100.00
IF	281	2	2	100.00
CASE	319	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	228	(lc_strap_sample_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	230	(rv_strap_sample_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	234	(dft_strap_sample_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T19,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	408	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	403	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	408	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	398	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	399	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	408	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	403	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	408	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	403	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	394	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	408	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	403	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T45,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	266	if ((strap_en_q && tap_sampling_en))

Branches:

-1-	Status	Tests
1	Covered	T17,T19,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	272	if ((strap_en_q || tap_sampling_en))
-2-:	274	if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T17,T18,T19
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	281	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	319	case (tap_strap)
-2-:	326	if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel]))
-3-:	333	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[DftEnTapSel]))

Branches:

-1-	-2-	-3-	Status	Tests
LcTapSel	-	-	Covered	T35,T45,T36
RvTapSel	1	-	Covered	T35,T43,T46
RvTapSel	0	-	Covered	T588,T589,T590
DftTapSel	-	1	Covered	T43,T40,T47
DftTapSel	-	0	Covered	T48,T591,T592
default	-	-	Covered	T1,T2,T3

---

Assert Coverage for Module : pinmux_strap_sampling

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DftTapOff0_A	100082961	25895186	0	256
LcHwDebugEnClear_A	100082961	3768607	0	6
LcHwDebugEnSetRev0_A	100082961	1395	0	89
LcHwDebugEnSetRev1_A	100082961	1395	0	89
LcHwDebugEnSet_A	100082961	1395	0	0
RvTapOff0_A	100082961	253	0	178
RvTapOff1_A	100082961	23202240	0	0
TapStrapKnown_A	100082961	99427845	0	0
dft_strap0_idxRange_A	956	956	0	0
dft_strap1_idxRange_A	956	956	0	0
tap_strap0_idxRange_A	956	956	0	0
tap_strap1_idxRange_A	956	956	0	0
tck_idxRange_A	956	956	0	0
tdi_idxRange_A	956	956	0	0
tdo_idxRange_A	956	956	0	0
tms_idxRange_A	956	956	0	0
trst_idxRange_A	956	956	0	0

DftTapOff0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	25895186	0	256
T1	9760	9224	0	2
T2	10651	9389	0	2
T3	10145	9373	0	2
T59	10335	9391	0	2
T60	11039	9498	0	2
T61	9790	9099	0	2
T62	10336	9159	0	2
T63	10016	9191	0	2
T64	9678	9144	0	2
T65	9766	9234	0	2

LcHwDebugEnClear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	3768607	0	6
T7	41798	0	0	0
T20	147615	12214	0	0
T21	64181	0	0	0
T35	291302	1385	0	0
T36	0	1077	0	1
T37	0	10548	0	0
T38	0	4984	0	0
T39	0	4982	0	0
T44	0	10310	0	0
T45	62966	0	0	0
T75	0	4984	0	0
T77	123929	0	0	0
T78	37602	0	0	0
T79	27029	0	0	0
T80	20955	0	0	0
T86	116378	0	0	0
T116	0	0	0	1
T117	0	4983	0	0
T151	0	0	0	1
T201	0	5102	0	0
T330	0	0	0	1
T593	0	0	0	1
T594	0	0	0	1

LcHwDebugEnSetRev0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	1395	0	89
T7	41798	0	0	1
T17	539561	1	0	0
T18	54042	1	0	0
T19	54568	2	0	0
T20	147615	5	0	0
T35	291302	2	0	0
T36	0	0	0	1
T45	62966	1	0	0
T77	123929	5	0	0
T78	37602	1	0	0
T79	0	1	0	0
T86	116378	3	0	0
T110	0	0	0	1
T145	0	0	0	1
T150	0	0	0	1
T289	0	0	0	1
T303	0	0	0	1
T305	0	0	0	1
T326	0	0	0	1
T327	0	0	0	1

LcHwDebugEnSetRev1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	1395	0	89
T7	41798	0	0	1
T17	539561	1	0	0
T18	54042	1	0	0
T19	54568	2	0	0
T20	147615	5	0	0
T35	291302	2	0	0
T36	0	0	0	1
T45	62966	1	0	0
T77	123929	5	0	0
T78	37602	1	0	0
T79	0	1	0	0
T86	116378	3	0	0
T110	0	0	0	1
T145	0	0	0	1
T150	0	0	0	1
T289	0	0	0	1
T303	0	0	0	1
T305	0	0	0	1
T326	0	0	0	1
T327	0	0	0	1

LcHwDebugEnSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	1395	0	0
T7	41798	0	0	0
T17	539561	1	0	0
T18	54042	1	0	0
T19	54568	2	0	0
T20	147615	5	0	0
T35	291302	2	0	0
T45	62966	1	0	0
T77	123929	5	0	0
T78	37602	1	0	0
T79	0	1	0	0
T86	116378	3	0	0

RvTapOff0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	253	0	178
T1	9760	1	0	2
T2	10651	1	0	2
T3	10145	1	0	2
T59	10335	1	0	2
T60	11039	1	0	2
T61	9790	1	0	2
T62	10336	1	0	2
T63	10016	1	0	2
T64	9678	1	0	2
T65	9766	1	0	2

RvTapOff1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	23202240	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T62	10336	9163	0	0
T63	10016	9195	0	0
T64	9678	9148	0	0
T65	9766	9238	0	0

TapStrapKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100082961	99427845	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T62	10336	9163	0	0
T63	10016	9195	0	0
T64	9678	9148	0	0
T65	9766	9238	0	0

dft_strap0_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

dft_strap1_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

tap_strap0_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

tap_strap1_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

tck_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

tdi_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

tdo_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

tms_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

trst_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0