Unified Coverage Report :: Module :: usbdev_aon_wake

Module : usbdev_aon_wake

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.99	94.29	84.21			89.47	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake	91.99	94.29	84.21			89.47	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.99	94.29	84.21			89.47	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.09	97.83	90.32			96.23	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.73	99.00	87.94	98.66		84.58	88.46	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
filter_activity	100.00	100.00	100.00			100.00
filter_bus_reset	100.00	100.00	100.00			100.00
filter_sense	100.00	100.00	100.00			100.00
u_pullup_en_cdc	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_aon_wake

	Line No.	Total	Covered	Percent
TOTAL		35	33	94.29
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
ALWAYS	115	7	7	100.00
ALWAYS	127	6	5	83.33
ALWAYS	153	3	3	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	182	5	5	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	193	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
78	1	1
79	1	1
103	1	1
104	1	1
106	0	1
107	1	1
110	1	1
112	1	1
115	1	1
116	1	1
117	1	1
118	1	1
120	1	1
121	1	1
122	1	1
127	1	1
129	1	1
132	1	1
133	1	1
			MISSING_ELSE
141	1	1
142	0	1
			MISSING_ELSE
153	1	1
154	1	1
156	1	1
160	1	1
176	1	1
178	1	1
182	1	1
183	1	1
184	1	1
186	1	1
187	1	1
191	1	1
193	1	1

---

Cond Coverage for Module : usbdev_aon_wake

	Total	Covered	Percent
Conditions	38	32	84.21
Logical	38	32	84.21
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION ((usb_dp_i != usb_dppullup_en_o) | (usb_dn_i != usb_dnpullup_en_o))
             ---------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       53
 SUB-EXPRESSION (usb_dp_i != usb_dppullup_en_o)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       53
 SUB-EXPRESSION (usb_dn_i != usb_dnpullup_en_o)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((~usb_dp_i)) & ((~usb_dn_i)))
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       103
 EXPRESSION ((event_bus_reset | bus_reset_q) & wake_detect_active_q)
             ---------------1---------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T52
1	0	Covered	T3,T61,T62
1	1	Not Covered

 LINE       103
 SUB-EXPRESSION (event_bus_reset | bus_reset_q)
                 -------1-------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T61,T62

 LINE       104
 EXPRESSION ((event_sense_lost | sense_lost_q) & wake_detect_active_q)
             ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T33,T34,T52

 LINE       104
 SUB-EXPRESSION (event_sense_lost | sense_lost_q)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       110
 EXPRESSION (wake_detect_active_q & (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q))
             ----------1---------   ---------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T33,T34,T52

 LINE       110
 SUB-EXPRESSION (event_not_idle | event_bus_reset | event_sense_lost | wake_req_q)
                 -------1------   -------2-------   --------3-------   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Covered	T1,T2,T3
0	1	0	0	Covered	T3,T61,T49
1	0	0	0	Covered	T1,T2,T59

 LINE       176
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_aon)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T34,T52

 LINE       178
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_aon)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T34,T52

 LINE       191
 EXPRESSION (wake_detect_active_q ? aon_dppullup_en_q : usbdev_dppullup_en_i)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T34,T52

 LINE       193
 EXPRESSION (wake_detect_active_q ? aon_dnpullup_en_q : usbdev_dnpullup_en_i)
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T34,T52

---

Branch Coverage for Module : usbdev_aon_wake

	Line No.	Total	Covered	Percent
Branches		19	17	89.47
TERNARY	176	2	2	100.00
TERNARY	178	2	2	100.00
TERNARY	191	2	2	100.00
TERNARY	193	2	2	100.00
IF	115	2	2	100.00
CASE	129	5	3	60.00
IF	153	2	2	100.00
IF	182	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_aon_wake.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	176	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	(wake_detect_active_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T34,T52
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	129	case (wake_detect_active_q)
-2-:	132	if (suspend_req_aon_i)
-3-:	141	if (wake_ack_aon_i)

Branches:

-1-	-2-	-3-	Status	Tests
1'b0	1	-	Covered	T33,T34,T52
1'b0	0	-	Covered	T33,T34,T52
1'b1	-	1	Not Covered
1'b1	-	0	Covered	T33,T34,T52
default	-	-	Not Covered

	LineNo.	Expression
-1-:	153	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	if ((!rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_aon_wake

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
WakeDetectActiveAonKnown_A	1322107	1146331	0	0

WakeDetectActiveAonKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322107	1146331	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T62	315	91	0	0
T63	359	135	0	0
T64	464	240	0	0
T65	459	235	0	0