Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T230
0	1	Covered	T230,T231,T232
1	0	Covered	T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T230,T231
1	Covered	T8,T10,T230

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T230,T231
1	Covered	T8,T10,T230

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T230,T231,T232
1	1	Covered	T8,T230,T231

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T230
1	0	Covered	T8,T230,T231
1	1	Covered	T230,T231,T232

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T8,T230,T231

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T230
0	Covered	T8,T230,T231

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T230
0	Covered	T8,T230,T231

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	797105332	777722028	0	0
CheckNGreaterZero_A	1912	1912	0	0
GntImpliesReady_A	797105332	5342	0	0
GntImpliesValid_A	797105332	5342	0	0
GrantKnown_A	797105332	777722028	0	0
IdxKnown_A	797105332	777722028	0	0
IndexIsCorrect_A	797105332	5342	0	0
NoReadyValidNoGrant_A	797105332	0	0	0
Priority_A	797105332	5342	0	0
ReadyAndValidImplyGrant_A	797105332	5342	0	0
ReqAndReadyImplyGrant_A	797105332	5342	0	0
ReqImpliesValid_A	797105332	5342	0	0
ValidKnown_A	797105332	777722028	0	0
gen_data_port_assertion.DataFlow_A	797105332	5342	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	777722028	0	0
T7	329746	329550	0	0
T17	282208	282198	0	0
T18	437624	437398	0	0
T19	442724	442504	0	0
T20	1006638	1006062	0	0
T35	1204126	1203806	0	0
T45	373890	373788	0	0
T77	1011592	1011024	0	0
T78	297888	297662	0	0
T86	957416	957072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1912	1912	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T59	2	2	0	0
T60	2	2	0	0
T61	2	2	0	0
T62	2	2	0	0
T63	2	2	0	0
T64	2	2	0	0
T65	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	777722028	0	0
T7	329746	329550	0	0
T17	282208	282198	0	0
T18	437624	437398	0	0
T19	442724	442504	0	0
T20	1006638	1006062	0	0
T35	1204126	1203806	0	0
T45	373890	373788	0	0
T77	1011592	1011024	0	0
T78	297888	297662	0	0
T86	957416	957072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	777722028	0	0
T7	329746	329550	0	0
T17	282208	282198	0	0
T18	437624	437398	0	0
T19	442724	442504	0	0
T20	1006638	1006062	0	0
T35	1204126	1203806	0	0
T45	373890	373788	0	0
T77	1011592	1011024	0	0
T78	297888	297662	0	0
T86	957416	957072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	777722028	0	0
T7	329746	329550	0	0
T17	282208	282198	0	0
T18	437624	437398	0	0
T19	442724	442504	0	0
T20	1006638	1006062	0	0
T35	1204126	1203806	0	0
T45	373890	373788	0	0
T77	1011592	1011024	0	0
T78	297888	297662	0	0
T86	957416	957072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	5342	0	0
T230	142550	1783	0	0
T231	0	1783	0	0
T232	0	1776	0	0
T328	156922	0	0	0
T329	1259300	0	0	0
T330	149402	0	0	0
T331	255622	0	0	0
T332	175214	0	0	0
T333	536486	0	0	0
T334	260426	0	0	0
T335	285012	0	0	0
T336	385954	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T230
0	1	Covered	T230,T231,T232
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T230,T231,T232
1	Covered	T8,T10,T230

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T230,T231,T232
1	Covered	T8,T10,T230

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T230,T231,T232
1	1	Covered	T230,T231,T232

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T230
1	0	Covered	T230,T231,T232
1	1	Covered	T230,T231,T232

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T230,T231,T232

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T230
0	Covered	T230,T231,T232

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T230
0	Covered	T230,T231,T232

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398552666	388861014	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	398552666	4310	0	0
GntImpliesValid_A	398552666	4310	0	0
GrantKnown_A	398552666	388861014	0	0
IdxKnown_A	398552666	388861014	0	0
IndexIsCorrect_A	398552666	4310	0	0
NoReadyValidNoGrant_A	398552666	0	0	0
Priority_A	398552666	4310	0	0
ReadyAndValidImplyGrant_A	398552666	4310	0	0
ReqAndReadyImplyGrant_A	398552666	4310	0	0
ReqImpliesValid_A	398552666	4310	0	0
ValidKnown_A	398552666	388861014	0	0
gen_data_port_assertion.DataFlow_A	398552666	4310	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	4310	0	0
T230	71275	1439	0	0
T231	0	1439	0	0
T232	0	1432	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T230
0	1	Covered	T230,T231,T232
1	0	Covered	T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T230,T231
1	Covered	T8,T10,T230

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T8,T230,T231
1	Covered	T8,T10,T230

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T230,T231,T232
1	1	Covered	T8,T230,T231

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T230
1	0	Covered	T8,T230,T231
1	1	Covered	T230,T231,T232

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T8,T230,T231

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T230
0	Covered	T8,T230,T231

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T230
0	Covered	T8,T230,T231

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398552666	388861014	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	398552666	1032	0	0
GntImpliesValid_A	398552666	1032	0	0
GrantKnown_A	398552666	388861014	0	0
IdxKnown_A	398552666	388861014	0	0
IndexIsCorrect_A	398552666	1032	0	0
NoReadyValidNoGrant_A	398552666	0	0	0
Priority_A	398552666	1032	0	0
ReadyAndValidImplyGrant_A	398552666	1032	0	0
ReqAndReadyImplyGrant_A	398552666	1032	0	0
ReqImpliesValid_A	398552666	1032	0	0
ValidKnown_A	398552666	388861014	0	0
gen_data_port_assertion.DataFlow_A	398552666	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	388861014	0	0
T7	164873	164775	0	0
T17	141104	141099	0	0
T18	218812	218699	0	0
T19	221362	221252	0	0
T20	503319	503031	0	0
T35	602063	601903	0	0
T45	186945	186894	0	0
T77	505796	505512	0	0
T78	148944	148831	0	0
T86	478708	478536	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	1032	0	0
T230	71275	344	0	0
T231	0	344	0	0
T232	0	344	0	0
T328	78461	0	0	0
T329	629650	0	0	0
T330	74701	0	0	0
T331	127811	0	0	0
T332	87607	0	0	0
T333	268243	0	0	0
T334	130213	0	0	0
T335	142506	0	0	0
T336	192977	0	0	0