Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3770155	1			T29	2026		T30	1596		T31	79
values[2]	760820	1			T29	170		T30	441		T31	15
values[3]	108540	1			T30	9		T31	24		T313	5
values[4]	58598	1			T114	67		T132	2		T115	45
values[5]	40131	1			T114	60		T132	1		T115	50
values[6]	29655	1			T114	54		T132	6		T115	18
values[7]	23818	1			T114	48		T132	3		T115	5
values[8]	20289	1			T114	47		T132	1		T115	1
values[9]	17762	1			T114	61		T132	4		T115	3
values[10]	16486	1			T114	64		T132	2		T115	2
values[11]	15462	1			T114	61		T132	1		T115	1
values[12]	14639	1			T114	72		T132	4		T115	11
values[13]	13794	1			T114	70		T132	4		T115	16
values[14]	12714	1			T114	71		T115	17		T356	15
values[15]	12413	1			T114	53		T115	10		T356	15
values[16]	11657	1			T114	43		T115	4		T356	15
values[17]	11353	1			T114	37		T115	3		T356	15
values[18]	11230	1			T114	40		T115	15		T356	15
values[19]	11010	1			T114	44		T115	17		T356	15
values[20]	10474	1			T114	62		T115	14		T356	15
values[21]	10311	1			T114	68		T115	4		T356	15
values[22]	9687	1			T114	43		T115	12		T356	15
values[23]	9402	1			T114	65		T115	10		T356	15
values[24]	8955	1			T114	45		T115	8		T356	15
values[25]	8693	1			T114	34		T356	15		T411	2
values[26]	8157	1			T114	22		T356	15		T411	1
values[27]	8076	1			T114	21		T356	15		T411	1
values[28]	7923	1			T114	40		T356	15		T411	1
values[29]	7255	1			T114	63		T356	15		T411	1
values[30]	6688	1			T114	58		T356	15		T411	2
values[31]	6028	1			T114	56		T356	15		T411	1
values[32]	6006	1			T114	40		T356	15		T411	1
values[33]	5452	1			T114	20		T356	15		T411	2
values[34]	4812	1			T114	20		T356	15		T411	1
values[35]	4513	1			T114	27		T356	15		T411	3
values[36]	4277	1			T114	23		T356	15		T411	2
values[37]	4138	1			T114	9		T356	15		T411	3
values[38]	3877	1			T114	6		T356	15		T411	1
values[39]	3661	1			T114	4		T356	15		T411	1
values[40]	3641	1			T114	6		T356	15		T411	2
values[41]	3544	1			T114	8		T356	15		T411	1
values[42]	3407	1			T114	15		T356	15		T411	1
values[43]	3264	1			T114	8		T356	15		T411	1
values[44]	3180	1			T114	2		T356	15		T411	1
values[45]	3245	1			T114	5		T356	15		T411	1
values[46]	3112	1			T114	4		T356	17		T411	1
values[47]	3067	1			T114	3		T356	15		T411	2
values[48]	3062	1			T114	4		T356	15		T411	1
values[49]	2832	1			T114	1		T356	17		T411	1
values[50]	2809	1			T114	1		T356	16		T411	2
values[51]	2755	1			T114	3		T356	15		T411	2
values[52]	2664	1			T114	1		T356	16		T411	1
values[53]	2697	1			T114	1		T356	15		T411	3
values[54]	2466	1			T114	5		T356	16		T411	2
values[55]	2553	1			T114	2		T356	16		T411	1
values[56]	2451	1			T356	15		T411	1		T410	1
values[57]	2362	1			T356	15		T411	4		T410	1
values[58]	2369	1			T356	15		T411	1		T410	1
values[59]	2334	1			T356	15		T411	1		T410	2
values[60]	2376	1			T356	15		T411	1		T410	1
values[61]	2761	1			T356	15		T411	1		T410	1
values[62]	4228	1			T356	15		T411	1		T410	1
values[63]	16693	1			T356	147		T411	15		T410	8
values[64]	208263	1			T356	2800		T411	71		T410	109

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4870185	1			T29	2112		T30	1743		T31	85
values[2]	805203	1			T29	128		T30	349		T31	22
values[3]	75684	1			T30	27		T31	6		T59	2
values[4]	13025	1			T30	1		T31	1		T114	3
values[5]	5044	1			T357	11		T377	1		T356	19
values[6]	3178	1			T357	4		T356	10		T410	5
values[7]	2487	1			T357	1		T356	3		T410	7
values[8]	2083	1			T356	2		T410	4		T418	3
values[9]	1785	1			T356	2		T410	2		T418	6
values[10]	1643	1			T356	2		T410	2		T418	6
values[11]	1503	1			T356	2		T410	3		T418	5
values[12]	1489	1			T356	2		T410	7		T418	2
values[13]	1399	1			T356	2		T410	4		T418	3
values[14]	1304	1			T356	2		T410	3		T418	2
values[15]	1222	1			T356	2		T410	3		T418	4
values[16]	1316	1			T356	2		T410	4		T418	5
values[17]	1156	1			T356	2		T410	3		T418	3
values[18]	1002	1			T356	2		T410	4		T418	2
values[19]	1034	1			T356	2		T410	3		T418	3
values[20]	935	1			T356	2		T410	5		T418	4
values[21]	845	1			T356	2		T410	4		T418	4
values[22]	758	1			T356	2		T410	3		T418	4
values[23]	784	1			T356	2		T410	4		T418	4
values[24]	745	1			T356	2		T410	3		T418	9
values[25]	723	1			T356	2		T410	3		T418	11
values[26]	671	1			T356	2		T410	10		T418	3
values[27]	651	1			T356	2		T410	5		T418	3
values[28]	565	1			T356	3		T410	3		T418	2
values[29]	555	1			T356	2		T410	8		T418	2
values[30]	563	1			T356	2		T410	3		T418	5
values[31]	551	1			T356	2		T410	3		T418	3
values[32]	554	1			T356	2		T410	7		T418	5
values[33]	545	1			T356	2		T410	3		T418	4
values[34]	565	1			T356	2		T410	5		T418	2
values[35]	601	1			T356	2		T410	3		T418	4
values[36]	512	1			T356	2		T410	3		T418	3
values[37]	491	1			T356	2		T410	3		T418	8
values[38]	473	1			T356	2		T410	4		T418	5
values[39]	451	1			T356	3		T410	6		T418	6
values[40]	472	1			T356	2		T410	7		T418	5
values[41]	438	1			T356	2		T410	7		T418	4
values[42]	448	1			T356	2		T410	4		T418	5
values[43]	442	1			T356	2		T410	3		T418	2
values[44]	416	1			T356	2		T410	5		T418	6
values[45]	386	1			T356	2		T410	3		T418	5
values[46]	422	1			T356	2		T410	3		T418	5
values[47]	375	1			T356	2		T410	3		T418	2
values[48]	391	1			T356	2		T410	3		T418	7
values[49]	349	1			T356	2		T410	3		T418	8
values[50]	325	1			T356	2		T410	5		T418	4
values[51]	320	1			T356	2		T410	4		T418	3
values[52]	321	1			T356	2		T410	4		T418	2
values[53]	357	1			T356	2		T410	5		T418	2
values[54]	358	1			T356	2		T410	4		T418	5
values[55]	366	1			T356	2		T410	2		T418	3
values[56]	349	1			T356	2		T410	3		T418	3
values[57]	346	1			T356	2		T410	3		T418	2
values[58]	324	1			T356	2		T410	3		T418	3
values[59]	336	1			T356	2		T410	3		T418	5
values[60]	308	1			T356	2		T410	3		T418	2
values[61]	336	1			T356	2		T410	4		T418	4
values[62]	607	1			T356	2		T410	4		T418	5
values[63]	2821	1			T356	2		T410	12		T418	13
values[64]	23032	1			T356	356		T410	174		T418	202

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	603559	1			T29	22		T30	15		T31	1
values[2]	2700509	1			T29	2152		T30	750		T31	116
values[3]	1159545	1			T29	212		T30	1193		T31	41
values[4]	155175	1			T30	28		T31	4		T60	9
values[5]	77913	1			T114	62		T132	5		T115	104
values[6]	49417	1			T114	57		T132	7		T115	54
values[7]	35640	1			T114	43		T132	2		T115	17
values[8]	28445	1			T114	60		T132	2		T115	3
values[9]	24350	1			T114	71		T132	1		T115	8
values[10]	21400	1			T114	53		T132	1		T356	15
values[11]	19519	1			T114	29		T132	2		T356	15
values[12]	17781	1			T114	38		T132	3		T356	15
values[13]	16645	1			T114	47		T132	1		T356	15
values[14]	15869	1			T114	71		T132	2		T356	15
values[15]	14764	1			T114	74		T132	4		T356	15
values[16]	14592	1			T114	67		T132	1		T356	15
values[17]	14039	1			T114	69		T132	2		T356	15
values[18]	13788	1			T114	62		T132	2		T356	15
values[19]	12895	1			T114	50		T132	1		T356	15
values[20]	12447	1			T114	54		T132	3		T356	15
values[21]	11753	1			T114	47		T132	2		T356	15
values[22]	11488	1			T114	33		T132	3		T356	15
values[23]	10668	1			T114	35		T132	1		T356	15
values[24]	10158	1			T114	44		T132	2		T356	15
values[25]	9942	1			T114	70		T132	4		T356	16
values[26]	9571	1			T114	72		T132	2		T356	17
values[27]	9212	1			T114	60		T132	1		T356	15
values[28]	8695	1			T114	52		T132	4		T356	15
values[29]	8053	1			T114	38		T132	10		T356	15
values[30]	7609	1			T114	25		T132	4		T356	15
values[31]	7126	1			T114	31		T132	2		T356	15
values[32]	6474	1			T114	16		T132	5		T356	15
values[33]	6060	1			T114	16		T132	5		T356	16
values[34]	5514	1			T114	31		T132	5		T356	16
values[35]	5149	1			T114	30		T132	5		T356	16
values[36]	4751	1			T114	18		T132	4		T356	15
values[37]	4483	1			T114	15		T132	4		T356	15
values[38]	4259	1			T114	15		T132	1		T356	15
values[39]	3973	1			T114	9		T132	1		T356	15
values[40]	3832	1			T114	7		T132	3		T356	15
values[41]	3822	1			T114	2		T132	4		T356	15
values[42]	3585	1			T114	3		T132	1		T356	15
values[43]	3431	1			T114	1		T132	2		T356	15
values[44]	3423	1			T114	2		T132	3		T356	15
values[45]	3301	1			T132	1		T356	15		T419	3
values[46]	3176	1			T132	2		T356	15		T419	3
values[47]	3320	1			T132	1		T356	15		T419	5
values[48]	3324	1			T132	4		T356	15		T419	2
values[49]	3090	1			T132	4		T356	15		T419	3
values[50]	3241	1			T132	5		T356	15		T419	2
values[51]	3200	1			T132	9		T356	15		T419	2
values[52]	3005	1			T132	9		T356	15		T419	1
values[53]	2876	1			T132	2		T356	16		T419	1
values[54]	2807	1			T132	6		T356	15		T419	2
values[55]	2791	1			T132	4		T356	15		T419	3
values[56]	2792	1			T132	3		T356	16		T419	8
values[57]	2722	1			T132	2		T356	16		T419	2
values[58]	2679	1			T132	3		T356	15		T419	2
values[59]	2582	1			T132	5		T356	15		T419	3
values[60]	2543	1			T132	4		T356	16		T419	1
values[61]	2662	1			T132	1		T356	15		T419	3
values[62]	3848	1			T132	1		T356	15		T419	2
values[63]	17840	1			T356	217		T419	4		T411	2
values[64]	199056	1			T356	2519		T419	5		T411	40