Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1879529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23077137

1

T28

849

T1

1644

T2

1660

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15056146	1			T28	831		T17	1448		T18	13449
values[0x0]	8143065	1			T28	6		T1	1616		T2	1557
values[0x1]	1757455	1			T28	12		T1	1674		T2	1605

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	326114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24630552

1

T28

849

T1

2229

T2

2178

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11691745	1			T2	44		T3	42		T7	65
valid_sources[0x01]	11691021	1			T2	49		T3	47		T7	54
valid_sources[0x02]	25181	1			T2	48		T3	55		T7	50
valid_sources[0x03]	25262	1			T2	40		T3	66		T7	42
valid_sources[0x04]	25035	1			T2	71		T3	49		T7	37
valid_sources[0x05]	25382	1			T1	94		T2	59		T3	59
valid_sources[0x06]	24963	1			T2	55		T3	59		T7	52
valid_sources[0x07]	24784	1			T2	44		T3	60		T7	53
valid_sources[0x08]	25393	1			T2	40		T3	50		T7	54
valid_sources[0x09]	25160	1			T2	40		T3	48		T7	50
valid_sources[0x0a]	25394	1			T2	51		T3	57		T7	43
valid_sources[0x0b]	25025	1			T2	58		T3	42		T7	42
valid_sources[0x0c]	24889	1			T2	41		T3	53		T7	57
valid_sources[0x0d]	25635	1			T2	35		T3	41		T7	53
valid_sources[0x0e]	25868	1			T2	48		T3	67		T7	54
valid_sources[0x0f]	25282	1			T2	48		T3	66		T7	58
valid_sources[0x10]	24724	1			T2	41		T3	54		T7	48
valid_sources[0x11]	26030	1			T2	55		T3	67		T7	57
valid_sources[0x12]	25538	1			T2	42		T3	42		T7	57
valid_sources[0x13]	26173	1			T2	46		T3	61		T7	52
valid_sources[0x14]	25418	1			T2	70		T3	61		T7	58
valid_sources[0x15]	25591	1			T2	50		T3	49		T7	44
valid_sources[0x16]	25524	1			T2	57		T3	65		T7	47
valid_sources[0x17]	25199	1			T2	46		T3	50		T7	48
valid_sources[0x18]	25721	1			T2	53		T3	48		T7	53
valid_sources[0x19]	25561	1			T2	49		T3	57		T7	47
valid_sources[0x1a]	25142	1			T2	49		T3	50		T7	42
valid_sources[0x1b]	25453	1			T2	63		T3	68		T7	55
valid_sources[0x1c]	26596	1			T2	51		T3	45		T7	44
valid_sources[0x1d]	26147	1			T2	66		T3	47		T7	47
valid_sources[0x1e]	25519	1			T2	47		T3	64		T7	51
valid_sources[0x1f]	25320	1			T2	44		T3	70		T7	43
valid_sources[0x20]	25757	1			T2	48		T3	62		T7	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14721878

1

T28

831

T17

1448

T18

13449

values[0x0]

all_enables

biggest_size

8110036

1

T28

6

T1

1075

T2

1062

values[0x1]

all_enables

biggest_size

245223

1

T28

12

T1

569

T2

598

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2864278	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452903

1

T29

317

T30

14

T31

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1122672	1			T29	754		T30	51		T31	40
values[0x0]	1069282	1			T29	732		T30	7		T31	42
values[0x1]	1125227	1			T29	710		T30	53		T31	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2217793	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1099388

1

T29

724

T30

43

T31

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51741	1			T29	38		T30	2		T59	1
valid_sources[0x01]	52262	1			T29	51		T31	2		T59	1
valid_sources[0x02]	51125	1			T29	26		T30	4		T31	2
valid_sources[0x03]	51855	1			T29	34		T30	1		T59	4
valid_sources[0x04]	51822	1			T29	29		T30	3		T59	2
valid_sources[0x05]	51007	1			T29	24		T30	2		T59	3
valid_sources[0x06]	52325	1			T29	20		T31	5		T60	1
valid_sources[0x07]	52387	1			T29	24		T30	3		T59	2
valid_sources[0x08]	51051	1			T29	35		T30	1		T60	1
valid_sources[0x09]	51381	1			T29	23		T30	1		T60	4
valid_sources[0x0a]	52484	1			T29	18		T30	2		T60	5
valid_sources[0x0b]	52546	1			T29	42		T59	3		T60	2
valid_sources[0x0c]	51813	1			T29	28		T30	3		T59	1
valid_sources[0x0d]	52285	1			T29	53		T30	1		T59	6
valid_sources[0x0e]	51536	1			T29	40		T30	1		T59	2
valid_sources[0x0f]	51282	1			T29	39		T30	4		T31	12
valid_sources[0x10]	52057	1			T29	40		T60	5		T61	18
valid_sources[0x11]	51293	1			T29	28		T30	1		T31	6
valid_sources[0x12]	52291	1			T29	32		T59	1		T60	2
valid_sources[0x13]	51803	1			T29	52		T31	2		T59	8
valid_sources[0x14]	52002	1			T29	48		T30	4		T59	2
valid_sources[0x15]	52132	1			T29	31		T30	1		T59	1
valid_sources[0x16]	51924	1			T29	30		T30	3		T31	16
valid_sources[0x17]	51744	1			T29	32		T59	3		T60	4
valid_sources[0x18]	51225	1			T29	34		T30	3		T59	6
valid_sources[0x19]	53035	1			T29	20		T30	3		T31	2
valid_sources[0x1a]	51855	1			T29	31		T30	4		T31	1
valid_sources[0x1b]	52456	1			T29	39		T30	1		T60	5
valid_sources[0x1c]	50395	1			T29	31		T30	4		T59	2
valid_sources[0x1d]	50776	1			T29	19		T30	2		T59	3
valid_sources[0x1e]	51582	1			T29	30		T30	1		T59	3
valid_sources[0x1f]	51684	1			T29	36		T30	1		T59	2
valid_sources[0x20]	51532	1			T29	56		T30	2		T59	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47827

1

T29

29

T30

3

T59

3

values[0x0]

all_enables

biggest_size

357590

1

T29

259

T30

2

T31

10

values[0x1]

all_enables

biggest_size

47486

1

T29

29

T30

9

T31

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3058933	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

499190

1

T29

316

T30

13

T31

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1217807	1			T29	770		T30	30		T31	35
values[0x0]	1122194	1			T29	719		T30	8		T31	36
values[0x1]	1218122	1			T29	751		T30	44		T31	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2347146	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1210977

1

T29

774

T30

33

T31

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56048	1			T29	22		T31	2		T60	1
valid_sources[0x01]	55795	1			T29	29		T31	2		T59	9
valid_sources[0x02]	55377	1			T29	31		T31	2		T60	1
valid_sources[0x03]	54825	1			T29	36		T30	1		T61	5
valid_sources[0x04]	55300	1			T29	36		T60	2		T61	17
valid_sources[0x05]	55689	1			T29	45		T59	4		T60	2
valid_sources[0x06]	54119	1			T29	29		T31	7		T59	7
valid_sources[0x07]	56359	1			T29	39		T30	2		T59	11
valid_sources[0x08]	54864	1			T29	43		T30	1		T31	1
valid_sources[0x09]	55147	1			T29	25		T30	2		T31	1
valid_sources[0x0a]	56085	1			T29	37		T30	1		T31	2
valid_sources[0x0b]	56005	1			T29	21		T31	1		T61	14
valid_sources[0x0c]	56098	1			T29	43		T30	1		T31	4
valid_sources[0x0d]	56543	1			T29	31		T30	4		T60	9
valid_sources[0x0e]	55622	1			T29	36		T30	2		T31	3
valid_sources[0x0f]	55168	1			T29	33		T30	2		T59	19
valid_sources[0x10]	54790	1			T29	33		T30	1		T60	1
valid_sources[0x11]	55140	1			T29	39		T30	3		T59	1
valid_sources[0x12]	55992	1			T29	42		T30	2		T31	1
valid_sources[0x13]	56014	1			T29	29		T30	2		T31	5
valid_sources[0x14]	55468	1			T29	35		T30	1		T31	3
valid_sources[0x15]	55864	1			T29	31		T30	2		T59	17
valid_sources[0x16]	55411	1			T29	31		T30	1		T31	3
valid_sources[0x17]	55626	1			T29	27		T31	1		T61	19
valid_sources[0x18]	55747	1			T29	22		T30	1		T31	5
valid_sources[0x19]	57138	1			T29	39		T30	3		T60	5
valid_sources[0x1a]	54659	1			T29	30		T30	2		T60	7
valid_sources[0x1b]	56323	1			T29	35		T30	1		T31	7
valid_sources[0x1c]	54800	1			T29	27		T31	1		T61	28
valid_sources[0x1d]	55707	1			T29	40		T30	2		T31	4
valid_sources[0x1e]	55590	1			T29	43		T30	1		T59	6
valid_sources[0x1f]	56937	1			T29	43		T30	3		T31	1
valid_sources[0x20]	54797	1			T29	27		T59	1		T61	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52125

1

T29

33

T30

4

T59

2

values[0x0]

all_enables

biggest_size

394609

1

T29

254

T30

6

T31

15

values[0x1]

all_enables

biggest_size

52456

1

T29

29

T30

3

T31

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2891220	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

455791

1

T29

357

T30

10

T31

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1133961	1			T29	746		T30	42		T31	57
values[0x0]	1079345	1			T29	822		T30	8		T31	52
values[0x1]	1133705	1			T29	818		T30	40		T31	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2238411	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1108600

1

T29

805

T30

38

T31

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52555	1			T29	29		T30	2		T31	6
valid_sources[0x01]	52796	1			T29	44		T30	1		T31	2
valid_sources[0x02]	52432	1			T29	30		T30	3		T31	6
valid_sources[0x03]	52778	1			T29	35		T30	1		T31	3
valid_sources[0x04]	52509	1			T29	36		T30	3		T31	2
valid_sources[0x05]	51877	1			T29	40		T30	2		T31	1
valid_sources[0x06]	51462	1			T29	55		T30	2		T31	6
valid_sources[0x07]	52855	1			T29	47		T30	2		T31	6
valid_sources[0x08]	51472	1			T29	37		T30	1		T31	3
valid_sources[0x09]	52496	1			T29	47		T30	1		T31	4
valid_sources[0x0a]	53281	1			T29	23		T59	4		T60	1
valid_sources[0x0b]	53215	1			T29	21		T30	1		T31	1
valid_sources[0x0c]	52611	1			T29	31		T30	1		T59	2
valid_sources[0x0d]	52707	1			T29	28		T31	5		T59	2
valid_sources[0x0e]	51964	1			T29	46		T30	2		T31	3
valid_sources[0x0f]	52410	1			T29	37		T30	2		T31	5
valid_sources[0x10]	51624	1			T29	27		T30	1		T31	3
valid_sources[0x11]	51320	1			T29	38		T30	1		T31	1
valid_sources[0x12]	52717	1			T29	56		T30	1		T31	2
valid_sources[0x13]	52851	1			T29	39		T30	4		T31	5
valid_sources[0x14]	52346	1			T29	42		T30	1		T31	4
valid_sources[0x15]	52137	1			T29	48		T60	2		T61	5
valid_sources[0x16]	52872	1			T29	32		T30	2		T31	2
valid_sources[0x17]	52263	1			T29	34		T31	4		T59	1
valid_sources[0x18]	51222	1			T29	40		T31	4		T59	2
valid_sources[0x19]	53047	1			T29	40		T30	2		T31	2
valid_sources[0x1a]	51671	1			T29	32		T59	1		T60	2
valid_sources[0x1b]	52989	1			T29	43		T30	2		T31	1
valid_sources[0x1c]	51102	1			T29	29		T30	2		T31	1
valid_sources[0x1d]	51506	1			T29	42		T30	2		T31	2
valid_sources[0x1e]	52182	1			T29	39		T31	4		T59	1
valid_sources[0x1f]	52223	1			T29	24		T59	4		T60	3
valid_sources[0x20]	52418	1			T29	52		T30	3		T59	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48051

1

T29

29

T30

1

T31

5

values[0x0]

all_enables

biggest_size

359863

1

T29

299

T30

6

T31

15

values[0x1]

all_enables

biggest_size

47877

1

T29

29

T30

3

T31

4