Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.43			88.43

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_device	98.45			98.45

---

Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.45			98.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.45			98.45

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.17	89.96		92.56			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	65	54	83.08
Total Bits	432	382	88.43
Total Bits 0->1	216	191	88.43
Total Bits 1->0	216	191	88.43

Ports	65	54	83.08
Port Bits	432	382	88.43
Port Bits 0->1	216	191	88.43
Port Bits 1->0	216	191	88.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
tl_i.d_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[12:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_o.a_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
tl_o.d_error	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T29,T30,T60	Yes	T29,T30,T31	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T29,T30,T59	Yes	T29,T30,T59	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sd_o[3:0]	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tpm_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T135,*T136,*T137	Yes	T135,T136,T137	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T135,T136,T138	Yes	T135,T136,T137	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
intr_generic_rx_full_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_rx_watermark_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_tx_watermark_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_rx_error_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_generic_rx_overflow_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_tx_underflow_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T140,T135,T136	Yes	T140,T135,T136	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T140,T142,T34	Yes	T140,T142,T34	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T140,T143,T144	Yes	T140,T143,T144	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
sck_monitor_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device

	Total	Covered	Percent
Totals	55	54	98.18
Total Bits	388	382	98.45
Total Bits 0->1	194	191	98.45
Total Bits 1->0	194	191	98.45

Ports	55	54	98.18
Port Bits	388	382	98.45
Port Bits 0->1	194	191	98.45
Port Bits 1->0	194	191	98.45

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
tl_i.d_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[12:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_o.a_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
tl_o.d_error	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T29,T30,T60	Yes	T29,T30,T31	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T29,T30,T59	Yes	T29,T30,T59	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T133,T134	Yes	T62,T133,T134	OUTPUT
cio_sck_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_sd_o[3:0]	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tpm_csb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T135,*T136,*T137	Yes	T135,T136,T137	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.csb_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.csb	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.sck_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.sck	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T135,T136,T138	Yes	T135,T136,T137	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
intr_generic_rx_full_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_rx_watermark_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_tx_watermark_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_rx_error_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_generic_rx_overflow_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_generic_tx_underflow_o	Yes	Yes	T139,T140,T141	Yes	T139,T140,T141	OUTPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T140,T135,T136	Yes	T140,T135,T136	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T140,T142,T34	Yes	T140,T142,T34	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T140,T142,T32	Yes	T140,T142,T32	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T140,T143,T144	Yes	T140,T143,T144	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sck_monitor_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range