Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.98 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.98 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15521552100.00
ALWAYS6844100.00
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CONT_ASSIGN11911100.00
CONT_ASSIGN1649111100.00
CONT_ASSIGN1650511100.00
CONT_ASSIGN1653911100.00
CONT_ASSIGN1655311100.00
ALWAYS16559202202100.00
CONT_ASSIGN1676311100.00
ALWAYS1676711100.00
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CONT_ASSIGN1697411100.00
CONT_ASSIGN1697511100.00
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CONT_ASSIGN1747011100.00
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CONT_ASSIGN1752111100.00
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CONT_ASSIGN1760211100.00
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CONT_ASSIGN1787611100.00
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CONT_ASSIGN1788811100.00
CONT_ASSIGN1789011100.00
CONT_ASSIGN1789211100.00
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CONT_ASSIGN1789611100.00
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CONT_ASSIGN1791211100.00
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ALWAYS17919202202100.00
ALWAYS18125561561100.00
CONT_ASSIGN1930000
CONT_ASSIGN1930811100.00
CONT_ASSIGN1930911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16491 1 1
16505 1 1
16539 1 1
16553 1 1
16559 1 1
16560 1 1
16561 1 1
16562 1 1
16563 1 1
16564 1 1
16565 1 1
16566 1 1
16567 1 1
16568 1 1
16569 1 1
16570 1 1
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16572 1 1
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16577 1 1
16578 1 1
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16580 1 1
16581 1 1
16582 1 1
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16587 1 1
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16589 1 1
16590 1 1
16591 1 1
16592 1 1
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16680 1 1
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19225 1 1
19226 1 1
19227 1 1
19228 1 1
19229 1 1
19230 1 1
19231 1 1
19232 1 1
19233 1 1
19234 1 1
19235 1 1
19236 1 1
19237 1 1
19238 1 1
19239 1 1
19240 1 1
19241 1 1
19242 1 1
19246 1 1
19247 1 1
19248 1 1
19249 1 1
19250 1 1
19251 1 1
19252 1 1
19253 1 1
19254 1 1
19255 1 1
19256 1 1
19257 1 1
19258 1 1
19259 1 1
19260 1 1
19261 1 1
19262 1 1
19263 1 1
19264 1 1
19265 1 1
19266 1 1
19267 1 1
19268 1 1
19269 1 1
19270 1 1
19274 1 1
19278 1 1
19282 1 1
19286 1 1
19300 unreachable
19308 1 1
19309 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2013201199.90
Logical2013201199.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1674899.74
16749-16767100.00
16767100.00
16767-17254100.00
17257-1791399.75

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 207 207 100.00
TERNARY 16763 2 2 100.00
IF 68 3 3 100.00
CASE 18126 202 202 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16763 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T29,T31,T59
0 Covered T29,T30,T31


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T28,T1,T2
0 1 Covered T324,T85,T325
0 0 Covered T28,T1,T2


LineNo. Expression -1-: 18126 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T29,T30,T31
addr_hit[1] Covered T18,T100,T140
addr_hit[2] Covered T18,T100,T140
addr_hit[3] Covered T18,T100,T140
addr_hit[4] Covered T18,T100,T140
addr_hit[5] Covered T18,T100,T140
addr_hit[6] Covered T18,T100,T140
addr_hit[7] Covered T18,T100,T140
addr_hit[8] Covered T18,T100,T140
addr_hit[9] Covered T18,T216,T140
addr_hit[10] Covered T18,T216,T140
addr_hit[11] Covered T18,T216,T140
addr_hit[12] Covered T18,T216,T140
addr_hit[13] Covered T18,T216,T140
addr_hit[14] Covered T18,T216,T140
addr_hit[15] Covered T18,T216,T140
addr_hit[16] Covered T18,T216,T140
addr_hit[17] Covered T18,T267,T140
addr_hit[18] Covered T18,T267,T140
addr_hit[19] Covered T18,T267,T140
addr_hit[20] Covered T18,T267,T140
addr_hit[21] Covered T18,T267,T140
addr_hit[22] Covered T18,T267,T140
addr_hit[23] Covered T18,T267,T140
addr_hit[24] Covered T18,T267,T140
addr_hit[25] Covered T18,T140,T189
addr_hit[26] Covered T18,T140,T189
addr_hit[27] Covered T18,T140,T189
addr_hit[28] Covered T18,T140,T189
addr_hit[29] Covered T18,T140,T189
addr_hit[30] Covered T18,T140,T189
addr_hit[31] Covered T18,T140,T189
addr_hit[32] Covered T18,T140,T189
addr_hit[33] Covered T18,T140,T189
addr_hit[34] Covered T18,T140,T189
addr_hit[35] Covered T18,T140,T189
addr_hit[36] Covered T18,T140,T189
addr_hit[37] Covered T18,T140,T189
addr_hit[38] Covered T18,T140,T189
addr_hit[39] Covered T18,T140,T189
addr_hit[40] Covered T18,T140,T189
addr_hit[41] Covered T18,T140,T189
addr_hit[42] Covered T18,T140,T189
addr_hit[43] Covered T18,T140,T189
addr_hit[44] Covered T18,T140,T189
addr_hit[45] Covered T18,T140,T189
addr_hit[46] Covered T18,T140,T189
addr_hit[47] Covered T18,T140,T189
addr_hit[48] Covered T18,T140,T189
addr_hit[49] Covered T18,T140,T189
addr_hit[50] Covered T18,T140,T189
addr_hit[51] Covered T18,T140,T189
addr_hit[52] Covered T18,T140,T189
addr_hit[53] Covered T18,T140,T189
addr_hit[54] Covered T18,T140,T189
addr_hit[55] Covered T18,T140,T189
addr_hit[56] Covered T18,T140,T189
addr_hit[57] Covered T18,T140,T189
addr_hit[58] Covered T18,T140,T189
addr_hit[59] Covered T18,T140,T189
addr_hit[60] Covered T18,T140,T189
addr_hit[61] Covered T18,T140,T189
addr_hit[62] Covered T18,T140,T189
addr_hit[63] Covered T18,T140,T189
addr_hit[64] Covered T18,T140,T189
addr_hit[65] Covered T18,T139,T140
addr_hit[66] Covered T18,T139,T140
addr_hit[67] Covered T18,T139,T140
addr_hit[68] Covered T18,T139,T140
addr_hit[69] Covered T18,T139,T140
addr_hit[70] Covered T18,T139,T140
addr_hit[71] Covered T18,T140,T189
addr_hit[72] Covered T18,T140,T189
addr_hit[73] Covered T18,T140,T189
addr_hit[74] Covered T18,T140,T189
addr_hit[75] Covered T18,T140,T189
addr_hit[76] Covered T18,T140,T189
addr_hit[77] Covered T18,T256,T140
addr_hit[78] Covered T18,T256,T140
addr_hit[79] Covered T18,T256,T140
addr_hit[80] Covered T18,T256,T140
addr_hit[81] Covered T18,T256,T140
addr_hit[82] Covered T18,T256,T140
addr_hit[83] Covered T18,T256,T140
addr_hit[84] Covered T18,T256,T140
addr_hit[85] Covered T18,T140,T189
addr_hit[86] Covered T18,T256,T140
addr_hit[87] Covered T18,T140,T189
addr_hit[88] Covered T18,T140,T189
addr_hit[89] Covered T18,T140,T189
addr_hit[90] Covered T18,T140,T189
addr_hit[91] Covered T18,T140,T189
addr_hit[92] Covered T18,T140,T189
addr_hit[93] Covered T18,T140,T189
addr_hit[94] Covered T18,T140,T189
addr_hit[95] Covered T18,T140,T189
addr_hit[96] Covered T18,T140,T189
addr_hit[97] Covered T18,T140,T189
addr_hit[98] Covered T18,T140,T189
addr_hit[99] Covered T18,T140,T189
addr_hit[100] Covered T18,T140,T189
addr_hit[101] Covered T18,T140,T189
addr_hit[102] Covered T18,T140,T189
addr_hit[103] Covered T18,T140,T189
addr_hit[104] Covered T18,T140,T189
addr_hit[105] Covered T18,T140,T189
addr_hit[106] Covered T18,T140,T189
addr_hit[107] Covered T18,T140,T189
addr_hit[108] Covered T18,T140,T189
addr_hit[109] Covered T18,T140,T189
addr_hit[110] Covered T18,T140,T189
addr_hit[111] Covered T18,T140,T189
addr_hit[112] Covered T18,T140,T189
addr_hit[113] Covered T18,T140,T189
addr_hit[114] Covered T18,T140,T189
addr_hit[115] Covered T18,T140,T189
addr_hit[116] Covered T18,T140,T189
addr_hit[117] Covered T18,T140,T189
addr_hit[118] Covered T18,T140,T189
addr_hit[119] Covered T18,T140,T189
addr_hit[120] Covered T18,T140,T189
addr_hit[121] Covered T18,T140,T189
addr_hit[122] Covered T18,T140,T189
addr_hit[123] Covered T18,T140,T189
addr_hit[124] Covered T18,T140,T189
addr_hit[125] Covered T18,T140,T189
addr_hit[126] Covered T18,T140,T189
addr_hit[127] Covered T18,T41,T42
addr_hit[128] Covered T18,T41,T42
addr_hit[129] Covered T18,T41,T42
addr_hit[130] Covered T18,T41,T42
addr_hit[131] Covered T18,T140,T189
addr_hit[132] Covered T18,T140,T189
addr_hit[133] Covered T18,T140,T189
addr_hit[134] Covered T18,T140,T189
addr_hit[135] Covered T18,T140,T189
addr_hit[136] Covered T18,T140,T189
addr_hit[137] Covered T18,T140,T189
addr_hit[138] Covered T18,T140,T189
addr_hit[139] Covered T18,T140,T189
addr_hit[140] Covered T18,T140,T189
addr_hit[141] Covered T18,T140,T189
addr_hit[142] Covered T18,T140,T189
addr_hit[143] Covered T18,T140,T189
addr_hit[144] Covered T18,T140,T189
addr_hit[145] Covered T18,T140,T189
addr_hit[146] Covered T18,T140,T189
addr_hit[147] Covered T18,T140,T189
addr_hit[148] Covered T18,T140,T189
addr_hit[149] Covered T18,T140,T189
addr_hit[150] Covered T18,T140,T189
addr_hit[151] Covered T18,T140,T189
addr_hit[152] Covered T18,T145,T99
addr_hit[153] Covered T18,T147,T140
addr_hit[154] Covered T18,T140,T189
addr_hit[155] Covered T18,T41,T42
addr_hit[156] Covered T18,T41,T42
addr_hit[157] Covered T18,T140,T189
addr_hit[158] Covered T18,T140,T189
addr_hit[159] Covered T18,T161,T140
addr_hit[160] Covered T18,T161,T140
addr_hit[161] Covered T18,T161,T140
addr_hit[162] Covered T18,T161,T140
addr_hit[163] Covered T18,T161,T140
addr_hit[164] Covered T18,T140,T189
addr_hit[165] Covered T18,T140,T189
addr_hit[166] Covered T18,T140,T189
addr_hit[167] Covered T18,T140,T189
addr_hit[168] Covered T18,T140,T189
addr_hit[169] Covered T18,T140,T189
addr_hit[170] Covered T18,T140,T189
addr_hit[171] Covered T18,T104,T266
addr_hit[172] Covered T18,T140,T189
addr_hit[173] Covered T18,T140,T189
addr_hit[174] Covered T18,T140,T189
addr_hit[175] Covered T18,T140,T189
addr_hit[176] Covered T18,T140,T189
addr_hit[177] Covered T18,T140,T189
addr_hit[178] Covered T18,T140,T189
addr_hit[179] Covered T18,T140,T189
addr_hit[180] Covered T18,T140,T189
addr_hit[181] Covered T18,T140,T189
addr_hit[182] Covered T18,T140,T189
addr_hit[183] Covered T18,T140,T189
addr_hit[184] Covered T18,T140,T189
addr_hit[185] Covered T126,T127,T322
addr_hit[186] Covered T126,T127,T322
addr_hit[187] Covered T126,T127,T322
addr_hit[188] Covered T126,T127,T322
addr_hit[189] Covered T299,T309,T747
addr_hit[190] Covered T126,T127,T322
addr_hit[191] Covered T18,T100,T216
addr_hit[192] Covered T18,T140,T189
addr_hit[193] Covered T18,T256,T139
addr_hit[194] Covered T18,T41,T42
addr_hit[195] Covered T18,T147,T145
addr_hit[196] Covered T18,T161,T104
addr_hit[197] Covered T18,T147,T145
addr_hit[198] Covered T18,T147,T145
addr_hit[199] Covered T189,T96,T190
addr_hit[200] Covered T21,T22,T23
default Covered T29,T30,T31


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 404821390 159888 0 0
reAfterRv 404821390 159888 0 0
rePulse 404821390 94042 0 0
wePulse 404821390 65846 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 404821390 159888 0 0
T18 404057 763 0 0
T19 190817 0 0 0
T20 183427 0 0 0
T41 0 44 0 0
T42 0 44 0 0
T43 0 44 0 0
T98 318674 0 0 0
T99 157469 8 0 0
T100 261358 43 0 0
T145 142304 8 0 0
T147 241437 40 0 0
T148 84112 0 0 0
T193 147191 8 0 0
T216 0 45 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 404821390 159888 0 0
T18 404057 763 0 0
T19 190817 0 0 0
T20 183427 0 0 0
T41 0 44 0 0
T42 0 44 0 0
T43 0 44 0 0
T98 318674 0 0 0
T99 157469 8 0 0
T100 261358 43 0 0
T145 142304 8 0 0
T147 241437 40 0 0
T148 84112 0 0 0
T193 147191 8 0 0
T216 0 45 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 404821390 94042 0 0
T18 404057 289 0 0
T19 190817 0 0 0
T20 183427 0 0 0
T41 0 14 0 0
T42 0 14 0 0
T43 0 14 0 0
T98 318674 0 0 0
T99 157469 3 0 0
T100 261358 17 0 0
T145 142304 3 0 0
T147 241437 19 0 0
T148 84112 0 0 0
T193 147191 3 0 0
T216 0 18 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 404821390 65846 0 0
T18 404057 474 0 0
T19 190817 0 0 0
T20 183427 0 0 0
T41 0 30 0 0
T42 0 30 0 0
T43 0 30 0 0
T98 318674 0 0 0
T99 157469 5 0 0
T100 261358 26 0 0
T145 142304 5 0 0
T147 241437 21 0 0
T148 84112 0 0 0
T193 147191 5 0 0
T216 0 27 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%