Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T86,T13,T241
0	1	Covered	T86,T241,T243
1	0	Covered	T13,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T86,T13,T241
1	Covered	T86,T13,T241

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T86,T13,T241
1	Covered	T86,T13,T241

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T86,T241,T243
1	1	Covered	T86,T13,T241

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T86,T13,T241
1	0	Covered	T86,T13,T241
1	1	Covered	T86,T241,T243

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T86,T13,T241

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T13,T241
0	Covered	T86,T13,T241

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T13,T241
0	Covered	T86,T13,T241

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	658517098	639599764	0	0
CheckNGreaterZero_A	1884	1884	0	0
GntImpliesReady_A	658517098	5352	0	0
GntImpliesValid_A	658517098	5352	0	0
GrantKnown_A	658517098	639599764	0	0
IdxKnown_A	658517098	639599764	0	0
IndexIsCorrect_A	658517098	5352	0	0
NoReadyValidNoGrant_A	658517098	0	0	0
Priority_A	658517098	5352	0	0
ReadyAndValidImplyGrant_A	658517098	5352	0	0
ReqAndReadyImplyGrant_A	658517098	5352	0	0
ReqImpliesValid_A	658517098	5352	0	0
ValidKnown_A	658517098	639599764	0	0
gen_data_port_assertion.DataFlow_A	658517098	5352	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	639599764	0	0
T17	272822	272620	0	0
T18	808114	808012	0	0
T19	381634	381524	0	0
T20	366854	366642	0	0
T98	637348	637238	0	0
T99	314938	314822	0	0
T100	522716	522606	0	0
T145	284608	284498	0	0
T147	482874	482758	0	0
T148	168224	168114	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1884	1884	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T7	2	2	0	0
T67	2	2	0	0
T68	2	2	0	0
T69	2	2	0	0
T70	2	2	0	0
T71	2	2	0	0
T72	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	639599764	0	0
T17	272822	272620	0	0
T18	808114	808012	0	0
T19	381634	381524	0	0
T20	366854	366642	0	0
T98	637348	637238	0	0
T99	314938	314822	0	0
T100	522716	522606	0	0
T145	284608	284498	0	0
T147	482874	482758	0	0
T148	168224	168114	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	639599764	0	0
T17	272822	272620	0	0
T18	808114	808012	0	0
T19	381634	381524	0	0
T20	366854	366642	0	0
T98	637348	637238	0	0
T99	314938	314822	0	0
T100	522716	522606	0	0
T145	284608	284498	0	0
T147	482874	482758	0	0
T148	168224	168114	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	639599764	0	0
T17	272822	272620	0	0
T18	808114	808012	0	0
T19	381634	381524	0	0
T20	366854	366642	0	0
T98	637348	637238	0	0
T99	314938	314822	0	0
T100	522716	522606	0	0
T145	284608	284498	0	0
T147	482874	482758	0	0
T148	168224	168114	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	5352	0	0
T86	177874	1784	0	0
T87	432356	0	0	0
T88	630292	0	0	0
T89	297488	0	0	0
T90	550502	0	0	0
T91	549280	0	0	0
T92	314080	0	0	0
T93	503850	0	0	0
T241	0	1786	0	0
T243	0	1782	0	0
T244	181518	0	0	0
T245	232274	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T86,T13,T241
0	1	Covered	T86,T241,T243
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T86,T241,T243
1	Covered	T86,T13,T241

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T86,T241,T243
1	Covered	T86,T13,T241

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T86,T241,T243
1	1	Covered	T86,T241,T243

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T86,T13,T241
1	0	Covered	T86,T241,T243
1	1	Covered	T86,T241,T243

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T86,T241,T243

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T13,T241
0	Covered	T86,T241,T243

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T13,T241
0	Covered	T86,T241,T243

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	329258549	319799882	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	329258549	4320	0	0
GntImpliesValid_A	329258549	4320	0	0
GrantKnown_A	329258549	319799882	0	0
IdxKnown_A	329258549	319799882	0	0
IndexIsCorrect_A	329258549	4320	0	0
NoReadyValidNoGrant_A	329258549	0	0	0
Priority_A	329258549	4320	0	0
ReadyAndValidImplyGrant_A	329258549	4320	0	0
ReqAndReadyImplyGrant_A	329258549	4320	0	0
ReqImpliesValid_A	329258549	4320	0	0
ValidKnown_A	329258549	319799882	0	0
gen_data_port_assertion.DataFlow_A	329258549	4320	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	4320	0	0
T86	88937	1440	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	1442	0	0
T243	0	1438	0	0
T244	90759	0	0	0
T245	116137	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T86,T13,T241
0	1	Covered	T86,T241,T243
1	0	Covered	T13,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T86,T13,T241
1	Covered	T86,T13,T241

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T86,T13,T241
1	Covered	T86,T13,T241

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T86,T241,T243
1	1	Covered	T86,T13,T241

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T86,T13,T241
1	0	Covered	T86,T13,T241
1	1	Covered	T86,T241,T243

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T86,T13,T241

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T13,T241
0	Covered	T86,T13,T241

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T86,T13,T241
0	Covered	T86,T13,T241

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	329258549	319799882	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	329258549	1032	0	0
GntImpliesValid_A	329258549	1032	0	0
GrantKnown_A	329258549	319799882	0	0
IdxKnown_A	329258549	319799882	0	0
IndexIsCorrect_A	329258549	1032	0	0
NoReadyValidNoGrant_A	329258549	0	0	0
Priority_A	329258549	1032	0	0
ReadyAndValidImplyGrant_A	329258549	1032	0	0
ReqAndReadyImplyGrant_A	329258549	1032	0	0
ReqImpliesValid_A	329258549	1032	0	0
ValidKnown_A	329258549	319799882	0	0
gen_data_port_assertion.DataFlow_A	329258549	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	319799882	0	0
T17	136411	136310	0	0
T18	404057	404006	0	0
T19	190817	190762	0	0
T20	183427	183321	0	0
T98	318674	318619	0	0
T99	157469	157411	0	0
T100	261358	261303	0	0
T145	142304	142249	0	0
T147	241437	241379	0	0
T148	84112	84057	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1032	0	0
T86	88937	344	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T241	0	344	0	0
T243	0	344	0	0
T244	90759	0	0	0
T245	116137	0	0	0