Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	942	942	0	0
OutputsKnown_A	83570441	82949185	0	0
gen_no_flops.OutputDelay_A	83570441	82949185	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83570441	82949185	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0
T72	10439	9215	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83570441	82949185	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0
T72	10439	9215	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	942	942	0	0
OutputsKnown_A	83570441	82949185	0	0
gen_no_flops.OutputDelay_A	83570441	82949185	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83570441	82949185	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0
T72	10439	9215	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83570441	82949185	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0
T72	10439	9215	0	0