Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.59 99.59

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn0 99.50 99.50
tb.dut.top_earlgrey.u_edn1 99.58 99.58


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.50 99.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.50 99.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.17 89.96 92.56 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.17 89.96 92.56 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1206 1201 99.59
Total Bits 0->1 603 602 99.83
Total Bits 1->0 603 599 99.34

Ports 78 74 94.87
Port Bits 1206 1201 99.59
Port Bits 0->1 603 602 99.83
Port Bits 1->0 603 599 99.34

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
rst_ni Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
tl_i.d_ready Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_mask[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_address[6:0] Yes Yes T29,T30,*T59 Yes T29,T30,T59 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_valid Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_o.a_ready Yes Yes T30,T31,T60 Yes T29,T30,T31 OUTPUT
tl_o.d_error Yes Yes T29,T30,T31 Yes T29,T30,T59 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_data[31:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_sink Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_source[5:0] Yes Yes T29,T30,T61 Yes T29,T30,T31 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
edn_i[0].edn_req Yes Yes T98,T44,T170 Yes T98,T44,T170 INPUT
edn_i[1].edn_req Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
edn_i[2].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[3].edn_req Yes Yes T399,T400,T401 Yes T399,T400,T401 INPUT
edn_i[4].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[5].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[6].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[7].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T98,T44,T170 Yes T98,T44,T170 OUTPUT
edn_o[0].edn_fips Yes Yes T98,T112,T101 Yes T98,T104,T266 OUTPUT
edn_o[0].edn_ack Yes Yes T98,T44,T170 Yes T98,T44,T170 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[1].edn_fips No No Yes T104,T302,T316 OUTPUT
edn_o[1].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T98,T99,T100 Yes T18,T19,T98 OUTPUT
edn_o[2].edn_fips Yes Yes T101,T102,T103 Yes T104,T101,T102 OUTPUT
edn_o[2].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T399,T400,T401 Yes T399,T400,T401 OUTPUT
edn_o[3].edn_fips No No Yes T401,T402,T219 OUTPUT
edn_o[3].edn_ack Yes Yes T399,T400,T401 Yes T399,T400,T401 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T41,T105,T170 Yes T147,T148,T100 OUTPUT
edn_o[4].edn_fips No No Yes T374,T724,T725 OUTPUT
edn_o[4].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[5].edn_fips Yes Yes T98,T112,T726 Yes T98,T113,T112 OUTPUT
edn_o[5].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[6].edn_fips Yes Yes T98,T112,T101 Yes T98,T104,T266 OUTPUT
edn_o[6].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T20,T98,T145 Yes T18,T19,T20 OUTPUT
edn_o[7].edn_fips Yes Yes T98,T112,T101 Yes T98,T197,T198 OUTPUT
edn_o[7].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
csrng_cmd_i.genbits_fips Yes Yes T340,T727,T728 Yes T98,T113,T104 INPUT
csrng_cmd_i.genbits_valid Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T98,T113,T729 Yes T98,T113,T729 INPUT
alert_rx_i[0].ack_n Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
alert_rx_i[0].ack_p Yes Yes T729,T62,T63 Yes T729,T62,T63 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T308 Yes T62,T63,T65 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T65 Yes T62,T63,T308 INPUT
alert_rx_i[1].ack_n Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
alert_rx_i[1].ack_p Yes Yes T62,T730,T231 Yes T62,T730,T231 INPUT
alert_rx_i[1].ping_n Yes Yes T62,T63,T65 Yes T62,T63,T65 INPUT
alert_rx_i[1].ping_p Yes Yes T62,T63,T65 Yes T62,T63,T65 INPUT
alert_tx_o[0].alert_n Yes Yes T28,T1,T2 Yes T28,T1,T2 OUTPUT
alert_tx_o[0].alert_p Yes Yes T729,T62,T63 Yes T729,T62,T63 OUTPUT
alert_tx_o[1].alert_n Yes Yes T28,T1,T2 Yes T28,T1,T2 OUTPUT
alert_tx_o[1].alert_p Yes Yes T62,T730,T231 Yes T62,T730,T231 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T18,T274,T257 Yes T18,T274,T257 OUTPUT
intr_edn_fatal_err_o Yes Yes T18,T257,T262 Yes T18,T257,T262 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 73 93.59
Total Bits 1204 1198 99.50
Total Bits 0->1 602 601 99.83
Total Bits 1->0 602 597 99.17

Ports 78 73 93.59
Port Bits 1204 1198 99.50
Port Bits 0->1 602 601 99.83
Port Bits 1->0 602 597 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
rst_ni Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
tl_i.d_ready Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_mask[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_address[6:0] Yes Yes T29,T30,*T59 Yes T29,T30,T59 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_valid Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_o.a_ready Yes Yes T30,T31,T60 Yes T29,T30,T31 OUTPUT
tl_o.d_error Yes Yes T29,T30,T31 Yes T29,T30,T59 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_data[31:0] Yes Yes T29,T30,T59 Yes T29,T30,T31 OUTPUT
tl_o.d_sink Yes Yes T29,T30,T59 Yes T29,T30,T31 OUTPUT
tl_o.d_source[5:0] Yes Yes T29,T30,T61 Yes T29,T30,T31 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T29,T30,T59 Yes T29,T30,T31 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T29,*T30,*T31 Yes T29,T30,T59 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
edn_i[0].edn_req Yes Yes T44,T170,T171 Yes T44,T170,T171 INPUT
edn_i[1].edn_req Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
edn_i[2].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[3].edn_req Yes Yes T399,T400,T401 Yes T399,T400,T401 INPUT
edn_i[4].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[5].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[6].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_i[7].edn_req Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T44,T170,T171 Yes T44,T170,T171 OUTPUT
edn_o[0].edn_fips No No Yes T401,T402,T219 OUTPUT
edn_o[0].edn_ack Yes Yes T44,T170,T171 Yes T44,T170,T171 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[1].edn_fips No No Yes T104,T302,T316 OUTPUT
edn_o[1].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T98,T99,T100 Yes T18,T19,T98 OUTPUT
edn_o[2].edn_fips Yes Yes T101,T102,T103 Yes T104,T101,T102 OUTPUT
edn_o[2].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T399,T400,T401 Yes T399,T400,T401 OUTPUT
edn_o[3].edn_fips No No Yes T401,T402,T219 OUTPUT
edn_o[3].edn_ack Yes Yes T399,T400,T401 Yes T399,T400,T401 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T41,T105,T170 Yes T147,T148,T100 OUTPUT
edn_o[4].edn_fips No No Yes T374,T724,T725 OUTPUT
edn_o[4].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[5].edn_fips Yes Yes T98,T112,T726 Yes T98,T113,T112 OUTPUT
edn_o[5].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[6].edn_fips Yes Yes T98,T112,T101 Yes T98,T104,T266 OUTPUT
edn_o[6].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T20,T98,T145 Yes T18,T19,T20 OUTPUT
edn_o[7].edn_fips Yes Yes T98,T112,T101 Yes T98,T197,T198 OUTPUT
edn_o[7].edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
csrng_cmd_i.genbits_fips Yes Yes T340,T727,T728 Yes T98,T113,T104 INPUT
csrng_cmd_i.genbits_valid Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T98,T113,T729 Yes T98,T113,T729 INPUT
alert_rx_i[0].ack_n Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
alert_rx_i[0].ack_p Yes Yes T729,T62,T63 Yes T729,T62,T63 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T308 Yes T62,T63,T66 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T66 Yes T62,T63,T308 INPUT
alert_rx_i[1].ack_n Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
alert_rx_i[1].ack_p Yes Yes T62,T730,T63 Yes T62,T730,T63 INPUT
alert_rx_i[1].ping_n Yes Yes T62,T63,T65 Yes T62,T63,T66 INPUT
alert_rx_i[1].ping_p Yes Yes T62,T63,T66 Yes T62,T63,T65 INPUT
alert_tx_o[0].alert_n Yes Yes T28,T1,T2 Yes T28,T1,T2 OUTPUT
alert_tx_o[0].alert_p Yes Yes T729,T62,T63 Yes T729,T62,T63 OUTPUT
alert_tx_o[1].alert_n Yes Yes T28,T1,T2 Yes T28,T1,T2 OUTPUT
alert_tx_o[1].alert_p Yes Yes T62,T730,T63 Yes T62,T730,T63 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T18,T274,T257 Yes T18,T274,T257 OUTPUT
intr_edn_fatal_err_o Yes Yes T18,T257,T262 Yes T18,T257,T262 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 710 707 99.58
Total Bits 0->1 355 354 99.72
Total Bits 1->0 355 353 99.44

Ports 50 48 96.00
Port Bits 710 707 99.58
Port Bits 0->1 355 354 99.72
Port Bits 1->0 355 353 99.44

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
rst_ni Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
tl_i.d_ready Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_mask[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_address[6:0] Yes Yes T29,T30,T61 Yes T29,T30,T61 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_i.a_valid Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
tl_o.a_ready Yes Yes T30,T31,T60 Yes T29,T30,T31 OUTPUT
tl_o.d_error Yes Yes T29,T30,T31 Yes T29,T30,T59 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_data[31:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_sink Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_source[5:0] Yes Yes T29,T30,T61 Yes T29,T30,T31 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
edn_i[0].edn_req Yes Yes T98,T104,T266 Yes T98,T104,T266 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T98,T104,T266 Yes T98,T104,T266 OUTPUT
edn_o[0].edn_fips Yes Yes T98,T112,T101 Yes T98,T104,T266 OUTPUT
edn_o[0].edn_ack Yes Yes T98,T104,T266 Yes T98,T104,T266 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T98,T113,T104 Yes T98,T113,T104 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T98,T113,T104 Yes T98,T113,T104 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T98,T113,T104 Yes T98,T113,T104 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T98,T104,T266 Yes T98,T104,T266 INPUT
csrng_cmd_i.genbits_fips No No Yes T340,T727,T728 INPUT
csrng_cmd_i.genbits_valid Yes Yes T98,T113,T104 Yes T98,T113,T104 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T98,T113,T104 Yes T98,T113,T104 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T98,T112,T101 Yes T98,T112,T101 INPUT
alert_rx_i[0].ack_n Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
alert_rx_i[0].ack_p Yes Yes T62,T63,T21 Yes T62,T63,T21 INPUT
alert_rx_i[0].ping_n Yes Yes T62,T63,T65 Yes T62,T63,T65 INPUT
alert_rx_i[0].ping_p Yes Yes T62,T63,T65 Yes T62,T63,T65 INPUT
alert_rx_i[1].ack_n Yes Yes T28,T1,T2 Yes T28,T1,T2 INPUT
alert_rx_i[1].ack_p Yes Yes T62,T231,T731 Yes T62,T231,T731 INPUT
alert_rx_i[1].ping_n Yes Yes T62,T63,T65 Yes T62,T63,T65 INPUT
alert_rx_i[1].ping_p Yes Yes T62,T63,T65 Yes T62,T63,T65 INPUT
alert_tx_o[0].alert_n Yes Yes T28,T1,T2 Yes T28,T1,T2 OUTPUT
alert_tx_o[0].alert_p Yes Yes T62,T63,T21 Yes T62,T63,T21 OUTPUT
alert_tx_o[1].alert_n Yes Yes T28,T1,T2 Yes T28,T1,T2 OUTPUT
alert_tx_o[1].alert_p Yes Yes T62,T231,T731 Yes T62,T231,T731 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T18,T274,T257 Yes T18,T274,T257 OUTPUT
intr_edn_fatal_err_o Yes Yes T18,T257,T262 Yes T18,T257,T262 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%