Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T9,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T9,T13,T14
1	1	Covered	T9,T13,T14

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T9,T13,T14
1	-	Covered	T9,T15,T16

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T9,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T13,T14
1	1	Covered	T9,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T9,T13,T14
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T9,T13,T14
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	113227	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	284	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	113227	0	0
T9	32698	915	0	0
T10	36724	0	0	0
T13	0	479	0	0
T14	0	357	0	0
T15	0	1099	0	0
T16	0	754	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T27	0	617	0	0
T95	31332	0	0	0
T124	52980	0	0	0
T126	0	372	0	0
T127	0	3564	0	0
T128	0	315	0	0
T322	0	346	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	284	0	0
T9	32698	2	0	0
T10	36724	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	2	0	0
T16	0	2	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T27	0	2	0	0
T95	31332	0	0	0
T124	52980	0	0	0
T126	0	1	0	0
T127	0	9	0	0
T128	0	1	0	0
T322	0	1	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T357,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T126
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	102089	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	257	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	102089	0	0
T13	432545	465	0	0
T14	0	264	0	0
T126	0	415	0	0
T127	0	3125	0	0
T128	0	285	0	0
T225	37698	0	0	0
T322	0	1904	0	0
T323	0	1995	0	0
T352	0	2967	0	0
T361	0	4077	0	0
T362	0	725	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	257	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	8	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	5	0	0
T323	0	5	0	0
T352	0	7	0	0
T361	0	11	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T375,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T126
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	119939	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	300	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	119939	0	0
T13	432545	378	0	0
T14	0	316	0	0
T126	0	437	0	0
T127	0	2683	0	0
T128	0	352	0	0
T225	37698	0	0	0
T322	0	1918	0	0
T323	0	3199	0	0
T352	0	4512	0	0
T361	0	4155	0	0
T362	0	698	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	300	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	7	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	5	0	0
T323	0	8	0	0
T352	0	11	0	0
T361	0	11	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T358,T359,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T126
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	104651	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	262	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	104651	0	0
T13	432545	428	0	0
T14	0	261	0	0
T126	0	434	0	0
T127	0	334	0	0
T128	0	288	0	0
T225	37698	0	0	0
T322	0	2470	0	0
T323	0	5268	0	0
T352	0	895	0	0
T361	0	4072	0	0
T362	0	711	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	262	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	6	0	0
T323	0	13	0	0
T352	0	2	0	0
T361	0	11	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T376,T8,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T14
1	-	Covered	T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	108587	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	271	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	108587	0	0
T8	21774	988	0	0
T13	0	452	0	0
T14	0	263	0	0
T85	36541	0	0	0
T86	22378	0	0	0
T87	54918	0	0	0
T88	78332	0	0	0
T89	40468	0	0	0
T90	101550	0	0	0
T91	67226	0	0	0
T92	42927	0	0	0
T93	61669	0	0	0
T126	0	407	0	0
T127	0	3594	0	0
T128	0	310	0	0
T322	0	2745	0	0
T323	0	4103	0	0
T361	0	1917	0	0
T362	0	649	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	271	0	0
T8	21774	2	0	0
T13	0	1	0	0
T14	0	1	0	0
T85	36541	0	0	0
T86	22378	0	0	0
T87	54918	0	0	0
T88	78332	0	0	0
T89	40468	0	0	0
T90	101550	0	0	0
T91	67226	0	0	0
T92	42927	0	0	0
T93	61669	0	0	0
T126	0	1	0	0
T127	0	9	0	0
T128	0	1	0	0
T322	0	7	0	0
T323	0	10	0	0
T361	0	5	0	0
T362	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T357,T377,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T126
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	93474	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	235	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	93474	0	0
T13	432545	417	0	0
T14	0	307	0	0
T126	0	473	0	0
T127	0	1529	0	0
T128	0	242	0	0
T225	37698	0	0	0
T322	0	3243	0	0
T323	0	1499	0	0
T352	0	1712	0	0
T361	0	1907	0	0
T362	0	693	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	235	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	4	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	8	0	0
T323	0	4	0	0
T352	0	4	0	0
T361	0	5	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T377,T10,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T10,T13,T14
1	-	Covered	T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T10,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T10,T13,T14
0	0	1	Covered	T10,T13,T14
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T10,T13,T14
0	0	1	Covered	T10,T13,T14
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	99916	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	251	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	99916	0	0
T5	25933	0	0	0
T10	36724	1005	0	0
T13	432545	434	0	0
T14	0	271	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T95	31332	0	0	0
T126	0	475	0	0
T127	0	2222	0	0
T128	0	336	0	0
T322	0	2011	0	0
T323	0	1517	0	0
T361	0	1533	0	0
T362	0	728	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	251	0	0
T5	25933	0	0	0
T10	36724	2	0	0
T13	432545	1	0	0
T14	0	1	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T95	31332	0	0	0
T126	0	1	0	0
T127	0	6	0	0
T128	0	1	0	0
T322	0	5	0	0
T323	0	4	0	0
T361	0	4	0	0
T362	0	2	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T126
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	106049	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	267	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	106049	0	0
T13	432545	442	0	0
T14	0	296	0	0
T126	0	369	0	0
T127	0	5512	0	0
T128	0	316	0	0
T225	37698	0	0	0
T322	0	4018	0	0
T323	0	2786	0	0
T352	0	1693	0	0
T361	0	4561	0	0
T362	0	727	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	267	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	14	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	10	0	0
T323	0	7	0	0
T352	0	4	0	0
T361	0	12	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T9,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T9,T13,T14
1	1	Covered	T9,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T9,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T13,T14
1	1	Covered	T9,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T9,T13,T14
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T9,T13,T14
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	121107	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	301	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	121107	0	0
T9	32698	421	0	0
T10	36724	0	0	0
T13	0	482	0	0
T14	0	257	0	0
T15	0	436	0	0
T16	0	382	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T27	0	243	0	0
T95	31332	0	0	0
T124	52980	0	0	0
T126	0	482	0	0
T127	0	1538	0	0
T128	0	322	0	0
T322	0	757	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	301	0	0
T9	32698	1	0	0
T10	36724	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T27	0	1	0	0
T95	31332	0	0	0
T124	52980	0	0	0
T126	0	1	0	0
T127	0	4	0	0
T128	0	1	0	0
T322	0	2	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	100654	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	253	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	100654	0	0
T13	432545	453	0	0
T14	0	343	0	0
T126	0	396	0	0
T127	0	1896	0	0
T128	0	344	0	0
T225	37698	0	0	0
T322	0	1086	0	0
T323	0	4020	0	0
T352	0	3631	0	0
T361	0	1207	0	0
T362	0	622	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	253	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	5	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	3	0	0
T323	0	10	0	0
T352	0	9	0	0
T361	0	3	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	111374	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	278	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	111374	0	0
T13	432545	475	0	0
T14	0	320	0	0
T126	0	375	0	0
T127	0	3922	0	0
T128	0	340	0	0
T225	37698	0	0	0
T322	0	2800	0	0
T323	0	5651	0	0
T352	0	3195	0	0
T361	0	6081	0	0
T362	0	754	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	278	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	10	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	7	0	0
T323	0	14	0	0
T352	0	8	0	0
T361	0	15	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	102232	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	257	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	102232	0	0
T13	432545	380	0	0
T14	0	292	0	0
T126	0	399	0	0
T127	0	290	0	0
T128	0	342	0	0
T225	37698	0	0	0
T322	0	1532	0	0
T323	0	5261	0	0
T352	0	1762	0	0
T361	0	5070	0	0
T362	0	827	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	257	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	4	0	0
T323	0	13	0	0
T352	0	4	0	0
T361	0	13	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T13,T14
1	1	Covered	T8,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T8,T13,T14
0	0	1	Covered	T8,T13,T14
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	111391	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	277	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	111391	0	0
T8	21774	449	0	0
T13	0	446	0	0
T14	0	344	0	0
T85	36541	0	0	0
T86	22378	0	0	0
T87	54918	0	0	0
T88	78332	0	0	0
T89	40468	0	0	0
T90	101550	0	0	0
T91	67226	0	0	0
T92	42927	0	0	0
T93	61669	0	0	0
T126	0	447	0	0
T127	0	1475	0	0
T128	0	318	0	0
T322	0	1186	0	0
T323	0	3817	0	0
T361	0	5563	0	0
T362	0	769	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	277	0	0
T8	21774	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T85	36541	0	0	0
T86	22378	0	0	0
T87	54918	0	0	0
T88	78332	0	0	0
T89	40468	0	0	0
T90	101550	0	0	0
T91	67226	0	0	0
T92	42927	0	0	0
T93	61669	0	0	0
T126	0	1	0	0
T127	0	4	0	0
T128	0	1	0	0
T322	0	3	0	0
T323	0	9	0	0
T361	0	14	0	0
T362	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	100397	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	251	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	100397	0	0
T13	432545	418	0	0
T14	0	346	0	0
T126	0	412	0	0
T127	0	606	0	0
T128	0	300	0	0
T225	37698	0	0	0
T322	0	834	0	0
T323	0	6493	0	0
T352	0	399	0	0
T361	0	1605	0	0
T362	0	723	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	251	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	2	0	0
T323	0	16	0	0
T352	0	1	0	0
T361	0	4	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T10,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T10,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T13,T14
1	1	Covered	T10,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T10,T13,T14
0	0	1	Covered	T10,T13,T14
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T10,T13,T14
0	0	1	Covered	T10,T13,T14
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	94567	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	237	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	94567	0	0
T5	25933	0	0	0
T10	36724	468	0	0
T13	432545	380	0	0
T14	0	320	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T95	31332	0	0	0
T126	0	419	0	0
T127	0	3130	0	0
T128	0	248	0	0
T322	0	783	0	0
T323	0	1472	0	0
T361	0	5230	0	0
T362	0	781	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	237	0	0
T5	25933	0	0	0
T10	36724	1	0	0
T13	432545	1	0	0
T14	0	1	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T95	31332	0	0	0
T126	0	1	0	0
T127	0	8	0	0
T128	0	1	0	0
T322	0	2	0	0
T323	0	4	0	0
T361	0	13	0	0
T362	0	2	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T377,T356,T378

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	107301	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	266	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	107301	0	0
T13	432545	440	0	0
T14	0	295	0	0
T126	0	448	0	0
T127	0	1849	0	0
T128	0	265	0	0
T225	37698	0	0	0
T322	0	2485	0	0
T323	0	3639	0	0
T352	0	2203	0	0
T361	0	883	0	0
T362	0	651	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	266	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	5	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	6	0	0
T323	0	9	0	0
T352	0	5	0	0
T361	0	2	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0