Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.71	97.30			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T379

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	100885	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	252	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	100885	0	0
T13	432545	454	0	0
T14	0	342	0	0
T126	0	396	0	0
T127	0	1033	0	0
T128	0	266	0	0
T225	37698	0	0	0
T322	0	3684	0	0
T323	0	3782	0	0
T352	0	455	0	0
T361	0	3440	0	0
T362	0	673	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	252	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	3	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	9	0	0
T323	0	9	0	0
T352	0	1	0	0
T361	0	9	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T11,T12,T13
0	0	1	Covered	T11,T12,T13
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	102060	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	256	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	102060	0	0
T11	29895	334	0	0
T12	0	324	0	0
T13	0	455	0	0
T14	0	337	0	0
T126	0	391	0	0
T127	0	1503	0	0
T128	0	294	0	0
T323	0	4020	0	0
T360	0	344	0	0
T361	0	3837	0	0
T380	65617	0	0	0
T381	189485	0	0	0
T382	95773	0	0	0
T383	67656	0	0	0
T384	121012	0	0	0
T385	21916	0	0	0
T386	36481	0	0	0
T387	65491	0	0	0
T388	393701	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	256	0	0
T11	29895	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	4	0	0
T128	0	1	0	0
T323	0	10	0	0
T361	0	10	0	0
T362	0	2	0	0
T380	65617	0	0	0
T381	189485	0	0	0
T382	95773	0	0	0
T383	67656	0	0	0
T384	121012	0	0	0
T385	21916	0	0	0
T386	36481	0	0	0
T387	65491	0	0	0
T388	393701	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T379

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	112005	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	280	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	112005	0	0
T13	432545	428	0	0
T14	0	316	0	0
T126	0	433	0	0
T128	0	286	0	0
T225	37698	0	0	0
T322	0	2380	0	0
T323	0	4415	0	0
T352	0	3292	0	0
T353	0	1698	0	0
T361	0	5923	0	0
T362	0	697	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	280	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	6	0	0
T323	0	11	0	0
T352	0	8	0	0
T353	0	5	0	0
T361	0	15	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	94919	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	239	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	94919	0	0
T13	432545	450	0	0
T14	0	336	0	0
T126	0	408	0	0
T127	0	597	0	0
T128	0	267	0	0
T225	37698	0	0	0
T322	0	4465	0	0
T323	0	4460	0	0
T352	0	2598	0	0
T361	0	4685	0	0
T362	0	664	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	239	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	11	0	0
T323	0	11	0	0
T352	0	6	0	0
T361	0	12	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T356,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	104807	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	262	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	104807	0	0
T13	432545	417	0	0
T14	0	244	0	0
T126	0	415	0	0
T127	0	611	0	0
T128	0	330	0	0
T225	37698	0	0	0
T322	0	4415	0	0
T323	0	1755	0	0
T352	0	1677	0	0
T361	0	5991	0	0
T362	0	769	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	262	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	11	0	0
T323	0	4	0	0
T352	0	4	0	0
T361	0	15	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T379

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	94845	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	238	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	94845	0	0
T13	432545	424	0	0
T14	0	325	0	0
T126	0	474	0	0
T127	0	1486	0	0
T128	0	319	0	0
T225	37698	0	0	0
T322	0	2728	0	0
T323	0	5224	0	0
T352	0	412	0	0
T361	0	1700	0	0
T362	0	675	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	238	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	4	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	7	0	0
T323	0	13	0	0
T352	0	1	0	0
T361	0	4	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	105785	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	264	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	105785	0	0
T13	432545	369	0	0
T14	0	345	0	0
T126	0	440	0	0
T127	0	2224	0	0
T128	0	262	0	0
T225	37698	0	0	0
T322	0	1489	0	0
T323	0	4180	0	0
T352	0	3594	0	0
T361	0	5600	0	0
T362	0	781	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	264	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	6	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	4	0	0
T323	0	10	0	0
T352	0	9	0	0
T361	0	14	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Unreachable
1	0	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T126
1	1	Covered	T13,T14,T126

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T13,T14,T126
0	0	1	Covered	T13,T14,T126
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	103651	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	260	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	103651	0	0
T13	432545	477	0	0
T14	0	353	0	0
T126	0	444	0	0
T127	0	1049	0	0
T128	0	269	0	0
T225	37698	0	0	0
T322	0	3621	0	0
T323	0	1175	0	0
T352	0	3649	0	0
T361	0	3055	0	0
T362	0	727	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	260	0	0
T13	432545	1	0	0
T14	0	1	0	0
T126	0	1	0	0
T127	0	3	0	0
T128	0	1	0	0
T225	37698	0	0	0
T322	0	9	0	0
T323	0	3	0	0
T352	0	9	0	0
T361	0	8	0	0
T362	0	2	0	0
T367	69572	0	0	0
T368	22172	0	0	0
T369	55952	0	0	0
T370	68818	0	0	0
T371	44762	0	0	0
T372	150711	0	0	0
T373	100863	0	0	0
T374	543221	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T356,T9,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T9,T13,T14
1	1	Covered	T9,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T1,T2
0	1	Covered	T8,T9,T10
1	0	Covered	T9,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T9,T13,T14
1	1	Covered	T9,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Not Covered
1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T9,T13,T14
0	0	1	Covered	T9,T13,T14
0	0	0	Covered	T28,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T1,T2
0	1	-	Covered	T9,T13,T14
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T28,T1,T2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	102593703	133318	0	0
DstReqKnown_A	1272825	1070046	0	0
SrcAckBusyChk_A	102593703	274	0	0
SrcBusyKnown_A	102593703	101855123	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	133318	0	0
T9	32698	1588	0	0
T10	36724	0	0	0
T13	0	379	0	0
T14	0	295	0	0
T16	0	2419	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T27	0	2176	0	0
T95	31332	0	0	0
T124	52980	0	0	0
T126	0	383	0	0
T127	0	2267	0	0
T128	0	293	0	0
T322	0	1416	0	0
T323	0	4763	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272825	1070046	0	0
T1	346	121	0	0
T2	368	142	0	0
T3	405	182	0	0
T7	351	125	0	0
T28	2076	1549	0	0
T67	304	78	0	0
T68	436	210	0	0
T69	400	177	0	0
T70	374	149	0	0
T71	359	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	274	0	0
T9	32698	3	0	0
T10	36724	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T16	0	5	0	0
T22	23869	0	0	0
T23	28361	0	0	0
T27	0	5	0	0
T95	31332	0	0	0
T124	52980	0	0	0
T126	0	1	0	0
T127	0	5	0	0
T128	0	1	0	0
T322	0	3	0	0
T323	0	9	0	0
T363	45357	0	0	0
T364	151936	0	0	0
T365	42210	0	0	0
T366	50322	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102593703	101855123	0	0
T1	10587	9475	0	0
T2	9908	9142	0	0
T3	10087	9397	0	0
T7	10080	9114	0	0
T28	64247	62148	0	0
T67	10506	9193	0	0
T68	9789	9162	0	0
T69	10128	9447	0	0
T70	9959	9287	0	0
T71	10069	9267	0	0