Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3678511	1			T32	93		T33	994		T34	103
values[2]	733072	1			T32	50		T33	290		T34	17
values[3]	101351	1			T32	1		T33	14		T55	1007
values[4]	53206	1			T55	582		T104	806		T370	1
values[5]	35168	1			T55	258		T104	385		T105	76
values[6]	26407	1			T55	145		T104	193		T105	60
values[7]	20923	1			T55	87		T104	141		T105	55
values[8]	18013	1			T55	68		T104	104		T105	55
values[9]	15982	1			T55	47		T104	118		T105	36
values[10]	14733	1			T55	43		T104	99		T105	49
values[11]	13431	1			T55	48		T104	66		T105	56
values[12]	12665	1			T55	24		T104	76		T105	77
values[13]	12043	1			T55	19		T104	51		T105	53
values[14]	11628	1			T55	15		T104	27		T105	64
values[15]	10661	1			T55	11		T104	31		T105	46
values[16]	10543	1			T55	12		T104	34		T105	45
values[17]	10210	1			T55	19		T104	27		T105	43
values[18]	9710	1			T55	14		T104	40		T105	47
values[19]	9589	1			T55	2		T104	30		T105	52
values[20]	9122	1			T55	6		T104	20		T105	42
values[21]	8867	1			T55	8		T104	18		T105	40
values[22]	8506	1			T55	5		T104	3		T105	33
values[23]	7858	1			T55	6		T104	5		T105	24
values[24]	8162	1			T55	9		T104	6		T105	35
values[25]	7827	1			T55	5		T104	7		T105	37
values[26]	7386	1			T55	9		T104	10		T105	29
values[27]	7006	1			T55	6		T104	8		T105	31
values[28]	6836	1			T55	4		T104	4		T105	35
values[29]	6543	1			T55	8		T104	5		T105	39
values[30]	5925	1			T55	8		T104	5		T105	33
values[31]	5582	1			T55	8		T104	4		T105	35
values[32]	5195	1			T55	11		T104	3		T105	25
values[33]	4759	1			T55	5		T104	3		T105	18
values[34]	4530	1			T55	3		T104	2		T105	25
values[35]	4381	1			T55	6		T104	4		T105	28
values[36]	4034	1			T55	6		T104	6		T105	10
values[37]	3775	1			T55	3		T104	8		T105	7
values[38]	3417	1			T55	6		T104	11		T105	12
values[39]	3310	1			T55	5		T104	8		T105	3
values[40]	3381	1			T55	9		T104	4		T105	8
values[41]	3255	1			T55	4		T104	1		T105	8
values[42]	3073	1			T55	5		T104	1		T105	7
values[43]	2994	1			T55	7		T104	4		T105	4
values[44]	3008	1			T55	7		T104	8		T105	5
values[45]	2808	1			T55	5		T104	4		T105	11
values[46]	2912	1			T55	5		T104	1		T105	3
values[47]	2859	1			T55	5		T104	1		T105	11
values[48]	2710	1			T55	5		T104	1		T105	7
values[49]	2646	1			T55	6		T104	3		T105	6
values[50]	2710	1			T55	8		T104	5		T105	18
values[51]	2693	1			T55	5		T104	3		T105	8
values[52]	2607	1			T55	3		T104	3		T105	2
values[53]	2600	1			T55	6		T104	7		T105	2
values[54]	2462	1			T55	6		T104	1		T105	2
values[55]	2427	1			T55	7		T104	1		T105	1
values[56]	2350	1			T55	9		T104	1		T105	1
values[57]	2328	1			T55	12		T104	1		T105	7
values[58]	2345	1			T55	3		T104	2		T105	3
values[59]	2238	1			T55	3		T104	4		T105	3
values[60]	2231	1			T55	7		T104	12		T105	2
values[61]	2526	1			T55	12		T104	6		T105	2
values[62]	4041	1			T55	19		T104	12		T105	2
values[63]	15874	1			T55	47		T104	15		T105	7
values[64]	201205	1			T55	50		T104	67		T105	124

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4672510	1			T32	80		T33	1118		T34	131
values[2]	768408	1			T32	20		T33	296		T34	36
values[3]	71743	1			T32	6		T33	56		T55	68
values[4]	12791	1			T32	2		T33	10		T55	12
values[5]	4989	1			T32	1		T55	16		T104	27
values[6]	3275	1			T55	17		T104	25		T105	3
values[7]	2419	1			T55	25		T104	14		T105	2
values[8]	1972	1			T55	8		T104	20		T105	1
values[9]	1660	1			T55	6		T104	11		T105	2
values[10]	1464	1			T55	11		T104	31		T105	2
values[11]	1350	1			T55	12		T104	32		T105	1
values[12]	1358	1			T55	3		T104	14		T105	3
values[13]	1182	1			T55	5		T104	8		T105	3
values[14]	1088	1			T55	21		T104	9		T105	2
values[15]	1033	1			T55	14		T104	12		T105	3
values[16]	1011	1			T55	12		T104	8		T105	4
values[17]	1015	1			T55	7		T104	6		T105	2
values[18]	890	1			T55	11		T105	3		T360	8
values[19]	823	1			T55	24		T105	3		T360	3
values[20]	786	1			T55	20		T105	1		T360	3
values[21]	848	1			T55	8		T105	3		T360	8
values[22]	742	1			T55	15		T105	2		T360	8
values[23]	727	1			T55	4		T105	1		T360	9
values[24]	668	1			T105	2		T360	9		T348	6
values[25]	738	1			T105	2		T360	8		T348	10
values[26]	685	1			T105	1		T360	11		T348	3
values[27]	700	1			T105	1		T360	13		T348	2
values[28]	614	1			T105	2		T360	7		T348	4
values[29]	584	1			T105	2		T360	10		T348	6
values[30]	530	1			T105	1		T360	4		T348	4
values[31]	521	1			T105	1		T360	1		T348	3
values[32]	534	1			T105	1		T360	1		T348	1
values[33]	588	1			T105	3		T360	1		T348	2
values[34]	538	1			T105	1		T360	4		T348	2
values[35]	528	1			T105	2		T360	1		T348	1
values[36]	526	1			T105	1		T360	3		T348	5
values[37]	514	1			T105	2		T360	8		T348	2
values[38]	516	1			T105	5		T360	4		T348	15
values[39]	454	1			T105	2		T348	7		T730	1
values[40]	413	1			T105	2		T348	1		T730	4
values[41]	438	1			T105	1		T348	5		T730	5
values[42]	402	1			T105	2		T348	2		T730	3
values[43]	427	1			T105	1		T348	3		T730	1
values[44]	409	1			T105	1		T348	2		T730	1
values[45]	403	1			T105	2		T348	1		T730	1
values[46]	390	1			T105	1		T348	1		T730	1
values[47]	425	1			T105	3		T348	1		T730	1
values[48]	397	1			T105	2		T348	1		T730	1
values[49]	362	1			T105	1		T348	1		T730	3
values[50]	411	1			T105	4		T348	4		T730	4
values[51]	413	1			T105	2		T348	6		T730	1
values[52]	369	1			T105	1		T348	4		T730	2
values[53]	347	1			T105	2		T348	1		T730	2
values[54]	335	1			T105	1		T348	1		T730	1
values[55]	366	1			T105	1		T348	1		T730	1
values[56]	354	1			T105	2		T348	3		T730	3
values[57]	350	1			T105	1		T348	2		T730	3
values[58]	332	1			T105	1		T348	3		T730	4
values[59]	354	1			T105	1		T348	2		T730	2
values[60]	325	1			T105	1		T348	3		T730	1
values[61]	411	1			T105	2		T348	2		T730	1
values[62]	680	1			T105	1		T348	4		T730	8
values[63]	3275	1			T105	5		T348	14		T730	82
values[64]	25917	1			T105	79		T348	12		T730	100

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	596362	1			T32	1		T33	12		T34	1
values[2]	2636606	1			T32	1		T33	467		T34	90
values[3]	1110393	1			T32	82		T33	898		T34	41
values[4]	138763	1			T32	30		T33	21		T55	842
values[5]	70757	1			T32	2		T55	488		T104	884
values[6]	46231	1			T55	282		T104	507		T105	53
values[7]	33842	1			T55	208		T104	276		T105	60
values[8]	26492	1			T55	185		T104	196		T105	45
values[9]	21208	1			T55	135		T104	120		T105	62
values[10]	18742	1			T55	121		T104	130		T105	62
values[11]	17289	1			T55	91		T104	113		T105	40
values[12]	15491	1			T55	42		T104	115		T105	45
values[13]	14674	1			T55	43		T104	90		T105	51
values[14]	14086	1			T55	21		T104	85		T105	50
values[15]	13030	1			T55	30		T104	54		T105	59
values[16]	12531	1			T55	18		T104	29		T105	42
values[17]	11970	1			T55	15		T104	19		T105	43
values[18]	11560	1			T55	10		T104	33		T105	38
values[19]	10906	1			T55	15		T104	28		T105	47
values[20]	10573	1			T55	18		T104	21		T105	72
values[21]	10450	1			T55	36		T104	12		T105	77
values[22]	10000	1			T55	20		T104	7		T105	73
values[23]	9397	1			T55	11		T104	11		T105	51
values[24]	8947	1			T55	9		T104	8		T105	45
values[25]	8922	1			T55	3		T104	8		T105	43
values[26]	8366	1			T55	5		T104	3		T105	44
values[27]	7845	1			T55	3		T104	8		T105	49
values[28]	7431	1			T55	3		T104	8		T105	40
values[29]	6754	1			T55	3		T104	7		T105	40
values[30]	6333	1			T55	8		T104	5		T105	29
values[31]	5878	1			T55	14		T104	9		T105	18
values[32]	5657	1			T55	2		T104	9		T105	17
values[33]	5152	1			T55	3		T104	6		T105	23
values[34]	4836	1			T55	4		T104	14		T105	23
values[35]	4513	1			T55	2		T104	11		T105	29
values[36]	4237	1			T55	3		T104	4		T105	15
values[37]	4129	1			T55	3		T104	3		T105	7
values[38]	3977	1			T55	7		T104	3		T105	12
values[39]	3799	1			T55	3		T104	5		T105	6
values[40]	3636	1			T55	7		T104	8		T105	10
values[41]	3553	1			T55	3		T104	3		T105	13
values[42]	3496	1			T55	2		T104	6		T105	10
values[43]	3364	1			T55	4		T104	6		T105	9
values[44]	3193	1			T55	10		T104	3		T105	7
values[45]	3116	1			T55	8		T104	3		T105	8
values[46]	3157	1			T55	9		T104	5		T105	5
values[47]	2988	1			T55	7		T104	5		T105	6
values[48]	2945	1			T55	6		T104	13		T105	6
values[49]	2924	1			T55	2		T104	8		T105	8
values[50]	2966	1			T55	9		T104	8		T105	11
values[51]	2903	1			T55	4		T104	5		T105	5
values[52]	2859	1			T55	4		T104	1		T105	16
values[53]	2858	1			T55	4		T104	6		T105	12
values[54]	2839	1			T55	5		T104	5		T105	4
values[55]	2711	1			T55	20		T104	5		T105	7
values[56]	2668	1			T55	16		T104	1		T105	3
values[57]	2554	1			T55	5		T104	6		T105	1
values[58]	2528	1			T55	5		T104	2		T105	2
values[59]	2589	1			T55	2		T104	3		T105	1
values[60]	2549	1			T55	5		T104	1		T105	1
values[61]	2622	1			T55	9		T104	1		T105	2
values[62]	3903	1			T55	32		T104	1		T105	1
values[63]	19296	1			T55	93		T104	6		T105	2
values[64]	187326	1			T55	96		T104	81		T105	158