Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2186939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25033413

1

T29

524

T30

4001

T31

49930

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17380570	1			T29	127		T30	5758		T31	24928
values[0x0]	8058947	1			T29	262		T30	2276		T31	12512
values[0x1]	1780835	1			T29	1589		T30	2303		T31	12490

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	552613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26667739

1

T29

1533

T30

5669

T31

49930

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12511544	1			T29	29		T30	109		T31	855
valid_sources[0x01]	12510606	1			T29	29		T30	190		T31	723
valid_sources[0x02]	35110	1			T29	24		T30	124		T31	791
valid_sources[0x03]	35634	1			T29	34		T30	134		T31	751
valid_sources[0x04]	35248	1			T29	28		T30	147		T31	769
valid_sources[0x05]	34473	1			T29	20		T30	177		T31	724
valid_sources[0x06]	35791	1			T29	34		T30	193		T31	743
valid_sources[0x07]	34978	1			T29	30		T30	235		T31	868
valid_sources[0x08]	35037	1			T29	35		T30	190		T31	754
valid_sources[0x09]	35192	1			T29	34		T30	226		T31	759
valid_sources[0x0a]	34441	1			T29	25		T30	164		T31	742
valid_sources[0x0b]	34997	1			T29	33		T30	183		T31	783
valid_sources[0x0c]	35069	1			T29	35		T30	112		T31	820
valid_sources[0x0d]	35143	1			T29	32		T30	163		T31	804
valid_sources[0x0e]	34923	1			T29	28		T30	138		T31	769
valid_sources[0x0f]	35517	1			T29	28		T30	170		T31	843
valid_sources[0x10]	35987	1			T29	29		T30	159		T31	795
valid_sources[0x11]	35379	1			T29	32		T30	168		T31	788
valid_sources[0x12]	35427	1			T29	42		T30	181		T31	779
valid_sources[0x13]	38768	1			T29	29		T30	118		T31	777
valid_sources[0x14]	35587	1			T29	29		T30	128		T31	763
valid_sources[0x15]	36061	1			T29	24		T30	169		T31	795
valid_sources[0x16]	35408	1			T29	42		T30	207		T31	827
valid_sources[0x17]	35427	1			T29	30		T30	136		T31	762
valid_sources[0x18]	35276	1			T29	26		T30	184		T31	755
valid_sources[0x19]	35213	1			T29	40		T30	111		T31	818
valid_sources[0x1a]	34742	1			T29	27		T30	200		T31	738
valid_sources[0x1b]	36425	1			T29	32		T30	119		T31	809
valid_sources[0x1c]	35293	1			T29	33		T30	214		T31	826
valid_sources[0x1d]	35216	1			T29	32		T30	143		T31	742
valid_sources[0x1e]	35204	1			T29	32		T30	89		T31	725
valid_sources[0x1f]	36092	1			T29	36		T30	175		T31	827
valid_sources[0x20]	35016	1			T29	34		T30	87		T31	807

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16759812

1

T29

117

T30

1515

T31

24928

values[0x0]

all_enables

biggest_size

8017564

1

T29

201

T30

1351

T31

12512

values[0x1]

all_enables

biggest_size

256037

1

T29

206

T30

1135

T31

12490

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2803592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

443051

1

T32

19

T33

181

T34

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1099054	1			T32	42		T33	431		T34	36
values[0x0]	1047688	1			T32	45		T33	433		T34	46
values[0x1]	1099901	1			T32	57		T33	434		T34	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2170748	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1075895

1

T32

50

T33

442

T34

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51179	1			T32	8		T33	18		T56	28
valid_sources[0x01]	50843	1			T32	15		T33	28		T56	18
valid_sources[0x02]	49849	1			T33	11		T56	41		T55	62
valid_sources[0x03]	50984	1			T32	3		T33	18		T56	11
valid_sources[0x04]	50378	1			T33	16		T56	36		T55	36
valid_sources[0x05]	50984	1			T33	27		T56	24		T55	35
valid_sources[0x06]	51338	1			T33	20		T56	40		T55	86
valid_sources[0x07]	50882	1			T32	1		T33	13		T34	6
valid_sources[0x08]	50588	1			T32	13		T33	22		T56	26
valid_sources[0x09]	50339	1			T33	29		T56	57		T55	84
valid_sources[0x0a]	50440	1			T33	24		T56	32		T55	80
valid_sources[0x0b]	49594	1			T33	7		T56	30		T55	95
valid_sources[0x0c]	50777	1			T32	15		T33	14		T56	16
valid_sources[0x0d]	50514	1			T33	21		T56	56		T55	101
valid_sources[0x0e]	51265	1			T32	4		T33	20		T56	24
valid_sources[0x0f]	50851	1			T33	26		T56	10		T55	69
valid_sources[0x10]	49124	1			T33	23		T56	29		T55	92
valid_sources[0x11]	51709	1			T33	11		T34	8		T56	9
valid_sources[0x12]	51436	1			T33	29		T56	22		T55	56
valid_sources[0x13]	50751	1			T32	1		T33	22		T56	39
valid_sources[0x14]	51294	1			T33	16		T56	37		T55	78
valid_sources[0x15]	50616	1			T32	3		T33	20		T34	1
valid_sources[0x16]	50906	1			T32	4		T33	22		T34	1
valid_sources[0x17]	51652	1			T33	14		T56	53		T55	40
valid_sources[0x18]	51124	1			T33	18		T56	46		T55	58
valid_sources[0x19]	50989	1			T32	21		T33	26		T34	7
valid_sources[0x1a]	51520	1			T33	24		T34	23		T55	72
valid_sources[0x1b]	50444	1			T33	33		T56	18		T55	24
valid_sources[0x1c]	51254	1			T33	16		T34	11		T56	14
valid_sources[0x1d]	50529	1			T33	32		T56	27		T55	73
valid_sources[0x1e]	50472	1			T33	22		T34	5		T56	48
valid_sources[0x1f]	50530	1			T32	4		T33	22		T34	20
valid_sources[0x20]	49881	1			T32	4		T33	23		T56	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46475

1

T32

2

T33

16

T34

2

values[0x0]

all_enables

biggest_size

349996

1

T32

15

T33

152

T34

11

values[0x1]

all_enables

biggest_size

46580

1

T32

2

T33

13

T34

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2988850	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

487623

1

T32

14

T33

213

T34

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1189133	1			T32	29		T33	519		T34	44
values[0x0]	1096094	1			T32	37		T33	477		T34	56
values[0x1]	1191246	1			T32	43		T33	484		T34	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2293810	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1182663

1

T32

41

T33

507

T34

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55024	1			T32	1		T33	26		T56	28
valid_sources[0x01]	55041	1			T32	2		T33	17		T34	2
valid_sources[0x02]	54296	1			T32	1		T33	20		T56	51
valid_sources[0x03]	52775	1			T32	3		T33	36		T56	16
valid_sources[0x04]	54001	1			T32	2		T33	26		T34	17
valid_sources[0x05]	55014	1			T32	2		T33	25		T56	25
valid_sources[0x06]	53770	1			T32	1		T33	23		T34	21
valid_sources[0x07]	55707	1			T32	4		T33	14		T56	77
valid_sources[0x08]	54927	1			T33	25		T34	3		T56	30
valid_sources[0x09]	54880	1			T32	1		T33	33		T56	52
valid_sources[0x0a]	53340	1			T33	25		T34	3		T56	31
valid_sources[0x0b]	54586	1			T32	4		T33	26		T56	29
valid_sources[0x0c]	53629	1			T32	2		T33	26		T56	13
valid_sources[0x0d]	55591	1			T32	1		T33	22		T56	49
valid_sources[0x0e]	54273	1			T33	20		T34	7		T56	35
valid_sources[0x0f]	53836	1			T33	20		T56	20		T55	59
valid_sources[0x10]	53591	1			T32	5		T33	14		T56	38
valid_sources[0x11]	54720	1			T32	1		T33	22		T56	19
valid_sources[0x12]	53292	1			T32	2		T33	18		T34	11
valid_sources[0x13]	53784	1			T33	19		T56	29		T55	26
valid_sources[0x14]	54016	1			T32	2		T33	22		T34	2
valid_sources[0x15]	53617	1			T32	4		T33	26		T34	9
valid_sources[0x16]	53880	1			T32	1		T33	22		T56	10
valid_sources[0x17]	55565	1			T32	5		T33	17		T34	6
valid_sources[0x18]	54344	1			T32	2		T33	24		T56	42
valid_sources[0x19]	54050	1			T32	1		T33	33		T56	38
valid_sources[0x1a]	53963	1			T32	1		T33	26		T55	69
valid_sources[0x1b]	54405	1			T32	2		T33	18		T56	22
valid_sources[0x1c]	53882	1			T32	3		T33	32		T56	6
valid_sources[0x1d]	54113	1			T32	1		T33	18		T34	2
valid_sources[0x1e]	55478	1			T33	20		T34	11		T56	66
valid_sources[0x1f]	54406	1			T32	2		T33	16		T56	21
valid_sources[0x20]	54040	1			T32	1		T33	32		T56	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51296

1

T32

1

T33

18

T34

3

values[0x0]

all_enables

biggest_size

385231

1

T32

10

T33

175

T34

20

values[0x1]

all_enables

biggest_size

51096

1

T32

3

T33

20

T34

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2820792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

446252

1

T32

17

T33

213

T34

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1105206	1			T32	42		T33	474		T34	42
values[0x0]	1054949	1			T32	33		T33	463		T34	49
values[0x1]	1106889	1			T32	41		T33	461		T34	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2183860	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1083184

1

T32

39

T33

471

T34

37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50851	1			T32	2		T33	23		T56	17
valid_sources[0x01]	51545	1			T33	30		T34	2		T56	16
valid_sources[0x02]	50664	1			T32	2		T33	3		T56	38
valid_sources[0x03]	51822	1			T32	4		T33	22		T34	1
valid_sources[0x04]	50370	1			T33	14		T34	1		T56	34
valid_sources[0x05]	51148	1			T32	1		T33	43		T34	2
valid_sources[0x06]	50468	1			T32	2		T33	28		T34	1
valid_sources[0x07]	50449	1			T32	6		T33	28		T56	76
valid_sources[0x08]	51044	1			T32	3		T33	21		T34	8
valid_sources[0x09]	51367	1			T32	1		T33	24		T34	3
valid_sources[0x0a]	50411	1			T33	40		T34	1		T56	37
valid_sources[0x0b]	50485	1			T32	1		T33	20		T34	1
valid_sources[0x0c]	51617	1			T32	1		T33	9		T34	3
valid_sources[0x0d]	50791	1			T32	2		T33	9		T56	49
valid_sources[0x0e]	51325	1			T33	15		T56	22		T55	62
valid_sources[0x0f]	50882	1			T32	5		T33	12		T56	15
valid_sources[0x10]	50640	1			T32	1		T33	14		T34	11
valid_sources[0x11]	52391	1			T33	22		T34	4		T56	7
valid_sources[0x12]	51266	1			T32	2		T33	15		T34	2
valid_sources[0x13]	50337	1			T32	4		T33	33		T56	22
valid_sources[0x14]	49768	1			T33	9		T34	1		T56	45
valid_sources[0x15]	50001	1			T32	1		T33	18		T34	1
valid_sources[0x16]	51034	1			T33	20		T34	3		T56	18
valid_sources[0x17]	51120	1			T32	5		T33	12		T34	1
valid_sources[0x18]	51269	1			T32	1		T33	15		T34	1
valid_sources[0x19]	51337	1			T32	1		T33	55		T56	25
valid_sources[0x1a]	49780	1			T32	2		T33	58		T34	2
valid_sources[0x1b]	50382	1			T32	6		T33	30		T34	6
valid_sources[0x1c]	51151	1			T32	2		T33	25		T34	6
valid_sources[0x1d]	50076	1			T32	1		T33	18		T34	7
valid_sources[0x1e]	51200	1			T33	27		T34	1		T56	47
valid_sources[0x1f]	51034	1			T33	22		T56	11		T55	73
valid_sources[0x20]	51420	1			T32	3		T33	20		T56	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47091

1

T32

1

T33

19

T56

32

values[0x0]

all_enables

biggest_size

352468

1

T32

14

T33

174

T34

15

values[0x1]

all_enables

biggest_size

46693

1

T32

2

T33

20

T34

2