Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.97 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.97 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15041504100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN1596311100.00
CONT_ASSIGN1597711100.00
CONT_ASSIGN1601111100.00
CONT_ASSIGN1602511100.00
ALWAYS16031196196100.00
CONT_ASSIGN1622911100.00
ALWAYS1623311100.00
CONT_ASSIGN1643211100.00
CONT_ASSIGN1643411100.00
CONT_ASSIGN1643511100.00
CONT_ASSIGN1643711100.00
CONT_ASSIGN1643811100.00
CONT_ASSIGN1644011100.00
CONT_ASSIGN1644111100.00
CONT_ASSIGN1644311100.00
CONT_ASSIGN1644411100.00
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CONT_ASSIGN1644711100.00
CONT_ASSIGN1644911100.00
CONT_ASSIGN1645011100.00
CONT_ASSIGN1645211100.00
CONT_ASSIGN1645311100.00
CONT_ASSIGN1645511100.00
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CONT_ASSIGN1646111100.00
CONT_ASSIGN1646211100.00
CONT_ASSIGN1646411100.00
CONT_ASSIGN1646511100.00
CONT_ASSIGN1646711100.00
CONT_ASSIGN1646811100.00
CONT_ASSIGN1647011100.00
CONT_ASSIGN1647111100.00
CONT_ASSIGN1647311100.00
CONT_ASSIGN1647411100.00
CONT_ASSIGN1647611100.00
CONT_ASSIGN1647711100.00
CONT_ASSIGN1647911100.00
CONT_ASSIGN1648011100.00
CONT_ASSIGN1648211100.00
CONT_ASSIGN1648311100.00
CONT_ASSIGN1648511100.00
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CONT_ASSIGN1648911100.00
CONT_ASSIGN1649111100.00
CONT_ASSIGN1649211100.00
CONT_ASSIGN1649411100.00
CONT_ASSIGN1649511100.00
CONT_ASSIGN1649711100.00
CONT_ASSIGN1649811100.00
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CONT_ASSIGN1652111100.00
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CONT_ASSIGN1652811100.00
CONT_ASSIGN1653011100.00
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CONT_ASSIGN1658111100.00
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CONT_ASSIGN1658711100.00
CONT_ASSIGN1658811100.00
CONT_ASSIGN1659011100.00
CONT_ASSIGN1659111100.00
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CONT_ASSIGN1659411100.00
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CONT_ASSIGN1660211100.00
CONT_ASSIGN1660311100.00
CONT_ASSIGN1660511100.00
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CONT_ASSIGN1661111100.00
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CONT_ASSIGN1664111100.00
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CONT_ASSIGN1672811100.00
CONT_ASSIGN1672911100.00
CONT_ASSIGN1673111100.00
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CONT_ASSIGN1673411100.00
CONT_ASSIGN1673511100.00
CONT_ASSIGN1673711100.00
CONT_ASSIGN1673811100.00
CONT_ASSIGN1674011100.00
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CONT_ASSIGN1675011100.00
CONT_ASSIGN1675211100.00
CONT_ASSIGN1675311100.00
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CONT_ASSIGN1676111100.00
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CONT_ASSIGN1676411100.00
CONT_ASSIGN1676511100.00
CONT_ASSIGN1676711100.00
CONT_ASSIGN1676811100.00
CONT_ASSIGN1677011100.00
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CONT_ASSIGN1679511100.00
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CONT_ASSIGN1688411100.00
CONT_ASSIGN1688511100.00
CONT_ASSIGN1688711100.00
CONT_ASSIGN1688811100.00
CONT_ASSIGN1689011100.00
CONT_ASSIGN1689111100.00
CONT_ASSIGN1689311100.00
CONT_ASSIGN1689411100.00
CONT_ASSIGN1689611100.00
CONT_ASSIGN1689711100.00
CONT_ASSIGN1689911100.00
CONT_ASSIGN1690011100.00
CONT_ASSIGN1690211100.00
CONT_ASSIGN1690311100.00
CONT_ASSIGN1690511100.00
CONT_ASSIGN1690611100.00
CONT_ASSIGN1690811100.00
CONT_ASSIGN1690911100.00
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CONT_ASSIGN1691211100.00
CONT_ASSIGN1691411100.00
CONT_ASSIGN1691511100.00
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CONT_ASSIGN1691811100.00
CONT_ASSIGN1692011100.00
CONT_ASSIGN1692111100.00
CONT_ASSIGN1692311100.00
CONT_ASSIGN1692411100.00
CONT_ASSIGN1692611100.00
CONT_ASSIGN1692711100.00
CONT_ASSIGN1692911100.00
CONT_ASSIGN1693011100.00
CONT_ASSIGN1693211100.00
CONT_ASSIGN1693311100.00
CONT_ASSIGN1693511100.00
CONT_ASSIGN1693611100.00
CONT_ASSIGN1693811100.00
CONT_ASSIGN1693911100.00
CONT_ASSIGN1694111100.00
CONT_ASSIGN1694211100.00
CONT_ASSIGN1694411100.00
CONT_ASSIGN1694511100.00
CONT_ASSIGN1694711100.00
CONT_ASSIGN1694811100.00
CONT_ASSIGN1695011100.00
CONT_ASSIGN1695111100.00
CONT_ASSIGN1695311100.00
CONT_ASSIGN1695411100.00
CONT_ASSIGN1695611100.00
CONT_ASSIGN1695711100.00
CONT_ASSIGN1695911100.00
CONT_ASSIGN1696011100.00
CONT_ASSIGN1696211100.00
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CONT_ASSIGN1696511100.00
CONT_ASSIGN1696611100.00
CONT_ASSIGN1696811100.00
CONT_ASSIGN1696911100.00
CONT_ASSIGN1697111100.00
CONT_ASSIGN1697311100.00
CONT_ASSIGN1697511100.00
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CONT_ASSIGN1698711100.00
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CONT_ASSIGN1699111100.00
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CONT_ASSIGN1699511100.00
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CONT_ASSIGN1700511100.00
CONT_ASSIGN1700711100.00
CONT_ASSIGN1700911100.00
CONT_ASSIGN1701111100.00
CONT_ASSIGN1701311100.00
CONT_ASSIGN1701511100.00
CONT_ASSIGN1701711100.00
CONT_ASSIGN1701911100.00
CONT_ASSIGN1702111100.00
CONT_ASSIGN1702311100.00
CONT_ASSIGN1702511100.00
CONT_ASSIGN1702711100.00
CONT_ASSIGN1702911100.00
CONT_ASSIGN1703111100.00
CONT_ASSIGN1703311100.00
CONT_ASSIGN1703411100.00
CONT_ASSIGN1703611100.00
CONT_ASSIGN1703811100.00
CONT_ASSIGN1704011100.00
CONT_ASSIGN1704211100.00
CONT_ASSIGN1704411100.00
CONT_ASSIGN1704611100.00
CONT_ASSIGN1704811100.00
CONT_ASSIGN1705011100.00
CONT_ASSIGN1705211100.00
CONT_ASSIGN1705411100.00
CONT_ASSIGN1705611100.00
CONT_ASSIGN1705811100.00
CONT_ASSIGN1706011100.00
CONT_ASSIGN1706211100.00
CONT_ASSIGN1706411100.00
CONT_ASSIGN1706611100.00
CONT_ASSIGN1706811100.00
CONT_ASSIGN1707011100.00
CONT_ASSIGN1707211100.00
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CONT_ASSIGN1734011100.00
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CONT_ASSIGN1734311100.00
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ALWAYS17349196196100.00
ALWAYS17549543543100.00
CONT_ASSIGN1868800
CONT_ASSIGN1869611100.00
CONT_ASSIGN1869711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
15963 1 1
15977 1 1
16011 1 1
16025 1 1
16031 1 1
16032 1 1
16033 1 1
16034 1 1
16035 1 1
16036 1 1
16037 1 1
16038 1 1
16039 1 1
16040 1 1
16041 1 1
16042 1 1
16043 1 1
16044 1 1
16045 1 1
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16050 1 1
16051 1 1
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16053 1 1
16054 1 1
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16060 1 1
16061 1 1
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16063 1 1
16064 1 1
16065 1 1
16066 1 1
16067 1 1
16068 1 1
16069 1 1
16070 1 1
16071 1 1
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16075 1 1
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16077 1 1
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16080 1 1
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16083 1 1
16084 1 1
16085 1 1
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16191 1 1
16192 1 1
16193 1 1
16194 1 1
16195 1 1
16196 1 1
16197 1 1
16198 1 1
16199 1 1
16200 1 1
16201 1 1
16202 1 1
16203 1 1
16204 1 1
16205 1 1
16206 1 1
16207 1 1
16208 1 1
16209 1 1
16210 1 1
16211 1 1
16212 1 1
16213 1 1
16214 1 1
16215 1 1
16216 1 1
16217 1 1
16218 1 1
16219 1 1
16220 1 1
16221 1 1
16222 1 1
16223 1 1
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16226 1 1
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16233 1 1
16432 1 1
16434 1 1
16435 1 1
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16446 1 1
16447 1 1
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16450 1 1
16452 1 1
16453 1 1
16455 1 1
16456 1 1
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16464 1 1
16465 1 1
16467 1 1
16468 1 1
16470 1 1
16471 1 1
16473 1 1
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16476 1 1
16477 1 1
16479 1 1
16480 1 1
16482 1 1
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16485 1 1
16486 1 1
16488 1 1
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16491 1 1
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16494 1 1
16495 1 1
16497 1 1
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16500 1 1
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16506 1 1
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16510 1 1
16512 1 1
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16515 1 1
16516 1 1
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16525 1 1
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16660 1 1
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16680 1 1
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16699 1 1
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16710 1 1
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16713 1 1
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16725 1 1
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16752 1 1
16753 1 1
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16791 1 1
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16810 1 1
16812 1 1
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16815 1 1
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16860 1 1
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16882 1 1
16884 1 1
16885 1 1
16887 1 1
16888 1 1
16890 1 1
16891 1 1
16893 1 1
16894 1 1
16896 1 1
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16899 1 1
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16902 1 1
16903 1 1
16905 1 1
16906 1 1
16908 1 1
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16911 1 1
16912 1 1
16914 1 1
16915 1 1
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16924 1 1
16926 1 1
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16929 1 1
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16935 1 1
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16945 1 1
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16950 1 1
16951 1 1
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16981 1 1
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16985 1 1
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16991 1 1
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17001 1 1
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17009 1 1
17011 1 1
17013 1 1
17015 1 1
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17019 1 1
17021 1 1
17023 1 1
17025 1 1
17027 1 1
17029 1 1
17031 1 1
17033 1 1
17034 1 1
17036 1 1
17038 1 1
17040 1 1
17042 1 1
17044 1 1
17046 1 1
17048 1 1
17050 1 1
17052 1 1
17054 1 1
17056 1 1
17058 1 1
17060 1 1
17062 1 1
17064 1 1
17066 1 1
17068 1 1
17070 1 1
17072 1 1
17074 1 1
17076 1 1
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17080 1 1
17082 1 1
17084 1 1
17086 1 1
17088 1 1
17090 1 1
17092 1 1
17094 1 1
17096 1 1
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17099 1 1
17101 1 1
17103 1 1
17105 1 1
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17111 1 1
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17117 1 1
17119 1 1
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17123 1 1
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17131 1 1
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17139 1 1
17141 1 1
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17214 1 1
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17222 1 1
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17330 1 1
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17364 1 1
17365 1 1
17366 1 1
17367 1 1
17368 1 1
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17370 1 1
17371 1 1
17372 1 1
17373 1 1
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17375 1 1
17376 1 1
17377 1 1
17378 1 1
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17380 1 1
17381 1 1
17382 1 1
17383 1 1
17384 1 1
17385 1 1
17386 1 1
17387 1 1
17388 1 1
17389 1 1
17390 1 1
17391 1 1
17392 1 1
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17399 1 1
17400 1 1
17401 1 1
17402 1 1
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17405 1 1
17406 1 1
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17410 1 1
17411 1 1
17412 1 1
17413 1 1
17414 1 1
17415 1 1
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17420 1 1
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17428 1 1
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17448 1 1
17449 1 1
17450 1 1
17451 1 1
17452 1 1
17453 1 1
17454 1 1
17455 1 1
17456 1 1
17457 1 1
17458 1 1
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17460 1 1
17461 1 1
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17464 1 1
17465 1 1
17466 1 1
17467 1 1
17468 1 1
17469 1 1
17470 1 1
17471 1 1
17472 1 1
17473 1 1
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17475 1 1
17476 1 1
17477 1 1
17478 1 1
17479 1 1
17480 1 1
17481 1 1
17482 1 1
17483 1 1
17484 1 1
17485 1 1
17486 1 1
17487 1 1
17488 1 1
17489 1 1
17490 1 1
17491 1 1
17492 1 1
17493 1 1
17494 1 1
17495 1 1
17496 1 1
17497 1 1
17498 1 1
17499 1 1
17500 1 1
17501 1 1
17502 1 1
17503 1 1
17504 1 1
17505 1 1
17506 1 1
17507 1 1
17508 1 1
17509 1 1
17510 1 1
17511 1 1
17512 1 1
17513 1 1
17514 1 1
17515 1 1
17516 1 1
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17518 1 1
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17520 1 1
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17522 1 1
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17552 1 1
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17560 1 1
17564 1 1
17568 1 1
17572 1 1
17576 1 1
17580 1 1
17584 1 1
17588 1 1
17592 1 1
17596 1 1
17600 1 1
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17608 1 1
17612 1 1
17616 1 1
17620 1 1
17624 1 1
17628 1 1
17632 1 1
17636 1 1
17640 1 1
17644 1 1
17648 1 1
17652 1 1
17656 1 1
17660 1 1
17664 1 1
17668 1 1
17672 1 1
17676 1 1
17680 1 1
17684 1 1
17688 1 1
17692 1 1
17696 1 1
17700 1 1
17704 1 1
17708 1 1
17712 1 1
17716 1 1
17720 1 1
17724 1 1
17728 1 1
17732 1 1
17736 1 1
17740 1 1
17744 1 1
17748 1 1
17752 1 1
17756 1 1
17760 1 1
17764 1 1
17768 1 1
17772 1 1
17776 1 1
17780 1 1
17784 1 1
17788 1 1
17792 1 1
17796 1 1
17800 1 1
17804 1 1
17808 1 1
17812 1 1
17816 1 1
17820 1 1
17824 1 1
17828 1 1
17832 1 1
17836 1 1
17840 1 1
17844 1 1
17848 1 1
17852 1 1
17856 1 1
17860 1 1
17864 1 1
17868 1 1
17872 1 1
17876 1 1
17880 1 1
17884 1 1
17888 1 1
17892 1 1
17896 1 1
17900 1 1
17904 1 1
17908 1 1
17912 1 1
17916 1 1
17920 1 1
17924 1 1
17928 1 1
17932 1 1
17936 1 1
17940 1 1
17944 1 1
17948 1 1
17952 1 1
17956 1 1
17960 1 1
17964 1 1
17968 1 1
17972 1 1
17976 1 1
17980 1 1
17984 1 1
17988 1 1
17992 1 1
17996 1 1
18000 1 1
18004 1 1
18008 1 1
18012 1 1
18016 1 1
18020 1 1
18024 1 1
18028 1 1
18032 1 1
18036 1 1
18040 1 1
18044 1 1
18048 1 1
18052 1 1
18056 1 1
18060 1 1
18064 1 1
18068 1 1
18072 1 1
18076 1 1
18080 1 1
18084 1 1
18088 1 1
18092 1 1
18096 1 1
18100 1 1
18104 1 1
18108 1 1
18112 1 1
18116 1 1
18120 1 1
18124 1 1
18128 1 1
18132 1 1
18136 1 1
18140 1 1
18144 1 1
18148 1 1
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18156 1 1
18160 1 1
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18168 1 1
18172 1 1
18176 1 1
18180 1 1
18184 1 1
18188 1 1
18192 1 1
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18200 1 1
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18216 1 1
18220 1 1
18224 1 1
18228 1 1
18232 1 1
18236 1 1
18240 1 1
18244 1 1
18248 1 1
18252 1 1
18256 1 1
18260 1 1
18264 1 1
18268 1 1
18269 1 1
18270 1 1
18271 1 1
18272 1 1
18273 1 1
18274 1 1
18275 1 1
18276 1 1
18277 1 1
18278 1 1
18279 1 1
18280 1 1
18281 1 1
18282 1 1
18283 1 1
18284 1 1
18285 1 1
18286 1 1
18287 1 1
18288 1 1
18289 1 1
18290 1 1
18291 1 1
18292 1 1
18293 1 1
18294 1 1
18295 1 1
18296 1 1
18297 1 1
18298 1 1
18299 1 1
18303 1 1
18304 1 1
18305 1 1
18306 1 1
18307 1 1
18308 1 1
18309 1 1
18310 1 1
18311 1 1
18312 1 1
18313 1 1
18314 1 1
18315 1 1
18316 1 1
18317 1 1
18318 1 1
18319 1 1
18320 1 1
18321 1 1
18322 1 1
18323 1 1
18324 1 1
18325 1 1
18326 1 1
18327 1 1
18328 1 1
18329 1 1
18330 1 1
18331 1 1
18332 1 1
18333 1 1
18334 1 1
18338 1 1
18339 1 1
18340 1 1
18341 1 1
18342 1 1
18343 1 1
18344 1 1
18345 1 1
18346 1 1
18347 1 1
18348 1 1
18349 1 1
18350 1 1
18351 1 1
18352 1 1
18353 1 1
18354 1 1
18355 1 1
18356 1 1
18357 1 1
18358 1 1
18359 1 1
18360 1 1
18361 1 1
18362 1 1
18363 1 1
18364 1 1
18365 1 1
18366 1 1
18367 1 1
18368 1 1
18369 1 1
18373 1 1
18374 1 1
18375 1 1
18376 1 1
18377 1 1
18378 1 1
18379 1 1
18380 1 1
18381 1 1
18382 1 1
18383 1 1
18384 1 1
18385 1 1
18386 1 1
18387 1 1
18388 1 1
18389 1 1
18390 1 1
18391 1 1
18392 1 1
18393 1 1
18394 1 1
18395 1 1
18396 1 1
18397 1 1
18398 1 1
18399 1 1
18400 1 1
18401 1 1
18402 1 1
18403 1 1
18404 1 1
18408 1 1
18409 1 1
18410 1 1
18411 1 1
18412 1 1
18413 1 1
18414 1 1
18415 1 1
18416 1 1
18417 1 1
18418 1 1
18419 1 1
18420 1 1
18421 1 1
18422 1 1
18423 1 1
18424 1 1
18425 1 1
18426 1 1
18427 1 1
18428 1 1
18429 1 1
18430 1 1
18431 1 1
18432 1 1
18433 1 1
18434 1 1
18435 1 1
18436 1 1
18437 1 1
18438 1 1
18439 1 1
18443 1 1
18444 1 1
18445 1 1
18446 1 1
18447 1 1
18448 1 1
18449 1 1
18450 1 1
18451 1 1
18452 1 1
18453 1 1
18454 1 1
18455 1 1
18456 1 1
18457 1 1
18458 1 1
18459 1 1
18460 1 1
18461 1 1
18465 1 1
18466 1 1
18467 1 1
18468 1 1
18469 1 1
18470 1 1
18471 1 1
18472 1 1
18473 1 1
18474 1 1
18475 1 1
18476 1 1
18477 1 1
18478 1 1
18479 1 1
18480 1 1
18481 1 1
18482 1 1
18483 1 1
18484 1 1
18485 1 1
18486 1 1
18487 1 1
18488 1 1
18489 1 1
18490 1 1
18491 1 1
18492 1 1
18493 1 1
18494 1 1
18495 1 1
18496 1 1
18500 1 1
18501 1 1
18502 1 1
18503 1 1
18504 1 1
18505 1 1
18506 1 1
18507 1 1
18508 1 1
18509 1 1
18510 1 1
18511 1 1
18512 1 1
18513 1 1
18514 1 1
18515 1 1
18516 1 1
18517 1 1
18518 1 1
18519 1 1
18520 1 1
18521 1 1
18522 1 1
18523 1 1
18524 1 1
18525 1 1
18526 1 1
18527 1 1
18528 1 1
18529 1 1
18530 1 1
18531 1 1
18535 1 1
18536 1 1
18537 1 1
18538 1 1
18539 1 1
18540 1 1
18541 1 1
18542 1 1
18543 1 1
18544 1 1
18545 1 1
18546 1 1
18547 1 1
18548 1 1
18549 1 1
18550 1 1
18551 1 1
18552 1 1
18553 1 1
18554 1 1
18555 1 1
18556 1 1
18557 1 1
18558 1 1
18559 1 1
18560 1 1
18561 1 1
18562 1 1
18563 1 1
18564 1 1
18565 1 1
18566 1 1
18570 1 1
18571 1 1
18572 1 1
18573 1 1
18574 1 1
18575 1 1
18576 1 1
18577 1 1
18578 1 1
18579 1 1
18580 1 1
18581 1 1
18582 1 1
18583 1 1
18584 1 1
18585 1 1
18586 1 1
18587 1 1
18588 1 1
18589 1 1
18590 1 1
18591 1 1
18592 1 1
18593 1 1
18594 1 1
18595 1 1
18596 1 1
18597 1 1
18598 1 1
18599 1 1
18600 1 1
18601 1 1
18605 1 1
18606 1 1
18607 1 1
18608 1 1
18609 1 1
18610 1 1
18611 1 1
18612 1 1
18613 1 1
18614 1 1
18615 1 1
18616 1 1
18617 1 1
18618 1 1
18619 1 1
18620 1 1
18621 1 1
18622 1 1
18623 1 1
18624 1 1
18625 1 1
18626 1 1
18627 1 1
18628 1 1
18629 1 1
18630 1 1
18631 1 1
18632 1 1
18633 1 1
18634 1 1
18635 1 1
18636 1 1
18640 1 1
18641 1 1
18642 1 1
18643 1 1
18644 1 1
18645 1 1
18646 1 1
18647 1 1
18648 1 1
18649 1 1
18650 1 1
18651 1 1
18652 1 1
18653 1 1
18654 1 1
18655 1 1
18656 1 1
18657 1 1
18658 1 1
18662 1 1
18666 1 1
18670 1 1
18674 1 1
18688 unreachable
18696 1 1
18697 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1953195199.90
Logical1953195199.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1622199.75
16222-16233100.00
16233-16432100.00
16435-16753100.00
16756-1734399.70

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 201 201 100.00
TERNARY 16229 2 2 100.00
IF 68 3 3 100.00
CASE 17550 196 196 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16229 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T32,T33,T34
0 Covered T32,T33,T34


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T29,T30,T31
0 1 Covered T304,T305,T306
0 0 Covered T29,T30,T31


LineNo. Expression -1-: 17550 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T32,T33,T34
addr_hit[1] Covered T29,T30,T31
addr_hit[2] Covered T29,T30,T31
addr_hit[3] Covered T29,T30,T31
addr_hit[4] Covered T29,T30,T31
addr_hit[5] Covered T29,T30,T31
addr_hit[6] Covered T29,T30,T31
addr_hit[7] Covered T29,T30,T31
addr_hit[8] Covered T29,T30,T31
addr_hit[9] Covered T29,T30,T31
addr_hit[10] Covered T29,T30,T31
addr_hit[11] Covered T29,T30,T31
addr_hit[12] Covered T29,T30,T31
addr_hit[13] Covered T29,T30,T31
addr_hit[14] Covered T29,T30,T31
addr_hit[15] Covered T29,T30,T31
addr_hit[16] Covered T29,T30,T31
addr_hit[17] Covered T29,T30,T31
addr_hit[18] Covered T29,T30,T31
addr_hit[19] Covered T29,T30,T31
addr_hit[20] Covered T29,T30,T31
addr_hit[21] Covered T29,T30,T31
addr_hit[22] Covered T29,T30,T31
addr_hit[23] Covered T29,T30,T31
addr_hit[24] Covered T29,T30,T31
addr_hit[25] Covered T29,T30,T31
addr_hit[26] Covered T29,T30,T31
addr_hit[27] Covered T29,T30,T31
addr_hit[28] Covered T29,T30,T31
addr_hit[29] Covered T29,T30,T31
addr_hit[30] Covered T29,T30,T31
addr_hit[31] Covered T29,T30,T31
addr_hit[32] Covered T29,T30,T31
addr_hit[33] Covered T29,T30,T31
addr_hit[34] Covered T29,T30,T31
addr_hit[35] Covered T29,T30,T31
addr_hit[36] Covered T29,T30,T31
addr_hit[37] Covered T29,T30,T31
addr_hit[38] Covered T29,T30,T31
addr_hit[39] Covered T29,T30,T31
addr_hit[40] Covered T29,T30,T31
addr_hit[41] Covered T29,T30,T31
addr_hit[42] Covered T29,T30,T31
addr_hit[43] Covered T29,T30,T31
addr_hit[44] Covered T29,T30,T31
addr_hit[45] Covered T29,T30,T31
addr_hit[46] Covered T29,T30,T31
addr_hit[47] Covered T29,T30,T31
addr_hit[48] Covered T29,T30,T31
addr_hit[49] Covered T29,T30,T31
addr_hit[50] Covered T29,T30,T31
addr_hit[51] Covered T29,T30,T31
addr_hit[52] Covered T29,T30,T31
addr_hit[53] Covered T29,T30,T31
addr_hit[54] Covered T29,T30,T31
addr_hit[55] Covered T29,T30,T31
addr_hit[56] Covered T29,T30,T31
addr_hit[57] Covered T29,T30,T31
addr_hit[58] Covered T29,T30,T31
addr_hit[59] Covered T29,T30,T31
addr_hit[60] Covered T29,T30,T31
addr_hit[61] Covered T29,T30,T31
addr_hit[62] Covered T29,T30,T31
addr_hit[63] Covered T29,T30,T31
addr_hit[64] Covered T29,T30,T31
addr_hit[65] Covered T29,T30,T31
addr_hit[66] Covered T29,T30,T31
addr_hit[67] Covered T29,T30,T31
addr_hit[68] Covered T29,T30,T31
addr_hit[69] Covered T29,T30,T31
addr_hit[70] Covered T29,T30,T31
addr_hit[71] Covered T29,T30,T31
addr_hit[72] Covered T29,T30,T31
addr_hit[73] Covered T29,T30,T31
addr_hit[74] Covered T29,T30,T31
addr_hit[75] Covered T29,T30,T31
addr_hit[76] Covered T29,T30,T31
addr_hit[77] Covered T29,T30,T31
addr_hit[78] Covered T29,T30,T31
addr_hit[79] Covered T29,T30,T31
addr_hit[80] Covered T29,T30,T31
addr_hit[81] Covered T29,T30,T31
addr_hit[82] Covered T29,T30,T31
addr_hit[83] Covered T29,T30,T31
addr_hit[84] Covered T29,T30,T31
addr_hit[85] Covered T29,T30,T31
addr_hit[86] Covered T29,T30,T31
addr_hit[87] Covered T29,T30,T31
addr_hit[88] Covered T29,T30,T31
addr_hit[89] Covered T29,T30,T31
addr_hit[90] Covered T29,T30,T31
addr_hit[91] Covered T29,T30,T31
addr_hit[92] Covered T29,T30,T31
addr_hit[93] Covered T29,T30,T31
addr_hit[94] Covered T29,T30,T31
addr_hit[95] Covered T29,T30,T31
addr_hit[96] Covered T29,T30,T31
addr_hit[97] Covered T29,T30,T31
addr_hit[98] Covered T29,T30,T31
addr_hit[99] Covered T29,T30,T31
addr_hit[100] Covered T29,T30,T31
addr_hit[101] Covered T29,T30,T31
addr_hit[102] Covered T29,T30,T31
addr_hit[103] Covered T29,T30,T31
addr_hit[104] Covered T29,T30,T31
addr_hit[105] Covered T29,T30,T31
addr_hit[106] Covered T29,T30,T31
addr_hit[107] Covered T29,T30,T31
addr_hit[108] Covered T29,T30,T31
addr_hit[109] Covered T29,T30,T31
addr_hit[110] Covered T29,T30,T31
addr_hit[111] Covered T29,T30,T31
addr_hit[112] Covered T29,T30,T31
addr_hit[113] Covered T29,T30,T31
addr_hit[114] Covered T29,T30,T31
addr_hit[115] Covered T29,T30,T31
addr_hit[116] Covered T29,T30,T31
addr_hit[117] Covered T29,T30,T31
addr_hit[118] Covered T29,T30,T31
addr_hit[119] Covered T29,T30,T31
addr_hit[120] Covered T29,T30,T31
addr_hit[121] Covered T29,T30,T31
addr_hit[122] Covered T29,T30,T31
addr_hit[123] Covered T29,T30,T31
addr_hit[124] Covered T29,T30,T31
addr_hit[125] Covered T29,T30,T31
addr_hit[126] Covered T29,T30,T31
addr_hit[127] Covered T29,T30,T31
addr_hit[128] Covered T29,T30,T31
addr_hit[129] Covered T29,T30,T31
addr_hit[130] Covered T29,T30,T31
addr_hit[131] Covered T29,T30,T31
addr_hit[132] Covered T29,T30,T31
addr_hit[133] Covered T29,T30,T31
addr_hit[134] Covered T29,T30,T31
addr_hit[135] Covered T29,T30,T31
addr_hit[136] Covered T29,T30,T31
addr_hit[137] Covered T29,T30,T31
addr_hit[138] Covered T29,T30,T31
addr_hit[139] Covered T29,T30,T31
addr_hit[140] Covered T29,T30,T31
addr_hit[141] Covered T29,T30,T31
addr_hit[142] Covered T29,T30,T31
addr_hit[143] Covered T29,T30,T31
addr_hit[144] Covered T29,T30,T31
addr_hit[145] Covered T29,T30,T31
addr_hit[146] Covered T29,T30,T31
addr_hit[147] Covered T29,T30,T31
addr_hit[148] Covered T29,T30,T31
addr_hit[149] Covered T29,T30,T31
addr_hit[150] Covered T29,T30,T31
addr_hit[151] Covered T29,T30,T31
addr_hit[152] Covered T29,T30,T31
addr_hit[153] Covered T29,T30,T31
addr_hit[154] Covered T29,T30,T31
addr_hit[155] Covered T29,T30,T31
addr_hit[156] Covered T29,T30,T31
addr_hit[157] Covered T29,T30,T31
addr_hit[158] Covered T29,T30,T31
addr_hit[159] Covered T29,T30,T31
addr_hit[160] Covered T29,T30,T31
addr_hit[161] Covered T29,T30,T31
addr_hit[162] Covered T29,T30,T31
addr_hit[163] Covered T29,T30,T31
addr_hit[164] Covered T29,T30,T31
addr_hit[165] Covered T29,T30,T31
addr_hit[166] Covered T29,T30,T31
addr_hit[167] Covered T29,T30,T31
addr_hit[168] Covered T29,T30,T31
addr_hit[169] Covered T29,T30,T31
addr_hit[170] Covered T29,T30,T31
addr_hit[171] Covered T29,T30,T31
addr_hit[172] Covered T29,T30,T31
addr_hit[173] Covered T29,T30,T31
addr_hit[174] Covered T29,T30,T31
addr_hit[175] Covered T29,T30,T31
addr_hit[176] Covered T29,T30,T31
addr_hit[177] Covered T29,T30,T31
addr_hit[178] Covered T29,T30,T31
addr_hit[179] Covered T29,T30,T31
addr_hit[180] Covered T29,T30,T31
addr_hit[181] Covered T29,T30,T31
addr_hit[182] Covered T29,T30,T31
addr_hit[183] Covered T29,T30,T31
addr_hit[184] Covered T29,T30,T31
addr_hit[185] Covered T29,T30,T31
addr_hit[186] Covered T29,T30,T31
addr_hit[187] Covered T29,T30,T31
addr_hit[188] Covered T29,T30,T31
addr_hit[189] Covered T29,T30,T31
addr_hit[190] Covered T29,T30,T31
addr_hit[191] Covered T29,T30,T31
addr_hit[192] Covered T29,T30,T31
addr_hit[193] Covered T29,T30,T31
addr_hit[194] Covered T29,T30,T31
default Covered T32,T33,T34


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 416219523 236271 0 0
reAfterRv 416219523 236271 0 0
rePulse 416219523 167219 0 0
wePulse 416219523 69052 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 416219523 236271 0 0
T18 154838 8 0 0
T19 89980 0 0 0
T20 237755 44 0 0
T21 233791 44 0 0
T29 189229 91 0 0
T30 325038 877 0 0
T31 264820 4247 0 0
T41 739788 603 0 0
T72 460206 15 0 0
T73 153066 10 0 0
T74 0 44 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 416219523 236271 0 0
T18 154838 8 0 0
T19 89980 0 0 0
T20 237755 44 0 0
T21 233791 44 0 0
T29 189229 91 0 0
T30 325038 877 0 0
T31 264820 4247 0 0
T41 739788 603 0 0
T72 460206 15 0 0
T73 153066 10 0 0
T74 0 44 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 416219523 167219 0 0
T18 154838 3 0 0
T19 89980 0 0 0
T20 237755 14 0 0
T21 233791 14 0 0
T30 325038 487 0 0
T31 264820 2089 0 0
T41 739788 282 0 0
T72 460206 5 0 0
T73 153066 3 0 0
T74 222948 14 0 0
T152 0 3 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 416219523 69052 0 0
T18 154838 5 0 0
T19 89980 0 0 0
T20 237755 30 0 0
T21 233791 30 0 0
T29 189229 91 0 0
T30 325038 390 0 0
T31 264820 2158 0 0
T41 739788 321 0 0
T72 460206 10 0 0
T73 153066 7 0 0
T74 0 30 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%