Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T11,T12
0	1	Covered	T145,T228,T229
1	0	Covered	T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T11,T228
1	Covered	T145,T11,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T11,T228
1	Covered	T145,T11,T12

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T228,T229
1	1	Covered	T145,T11,T228

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T11,T12
1	0	Covered	T145,T11,T228
1	1	Covered	T145,T228,T229

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T11,T228

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T11,T12
0	Covered	T145,T11,T228

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T11,T12
0	Covered	T145,T11,T228

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	678821586	661621976	0	0
CheckNGreaterZero_A	1896	1896	0	0
GntImpliesReady_A	678821586	5532	0	0
GntImpliesValid_A	678821586	5532	0	0
GrantKnown_A	678821586	661621976	0	0
IdxKnown_A	678821586	661621976	0	0
IndexIsCorrect_A	678821586	5532	0	0
NoReadyValidNoGrant_A	678821586	0	0	0
Priority_A	678821586	5532	0	0
ReadyAndValidImplyGrant_A	678821586	5532	0	0
ReqAndReadyImplyGrant_A	678821586	5532	0	0
ReqImpliesValid_A	678821586	5532	0	0
ValidKnown_A	678821586	661621976	0	0
gen_data_port_assertion.DataFlow_A	678821586	5532	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	661621976	0	0
T17	153360	153244	0	0
T18	309676	309566	0	0
T19	179960	179858	0	0
T20	475510	475284	0	0
T21	467582	467348	0	0
T41	1479576	1479006	0	0
T72	920412	920288	0	0
T73	306132	305944	0	0
T74	445896	445692	0	0
T75	228304	228194	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1896	1896	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T7	2	2	0	0
T60	2	2	0	0
T61	2	2	0	0
T62	2	2	0	0
T63	2	2	0	0
T64	2	2	0	0
T65	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	661621976	0	0
T17	153360	153244	0	0
T18	309676	309566	0	0
T19	179960	179858	0	0
T20	475510	475284	0	0
T21	467582	467348	0	0
T41	1479576	1479006	0	0
T72	920412	920288	0	0
T73	306132	305944	0	0
T74	445896	445692	0	0
T75	228304	228194	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	661621976	0	0
T17	153360	153244	0	0
T18	309676	309566	0	0
T19	179960	179858	0	0
T20	475510	475284	0	0
T21	467582	467348	0	0
T41	1479576	1479006	0	0
T72	920412	920288	0	0
T73	306132	305944	0	0
T74	445896	445692	0	0
T75	228304	228194	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	661621976	0	0
T17	153360	153244	0	0
T18	309676	309566	0	0
T19	179960	179858	0	0
T20	475510	475284	0	0
T21	467582	467348	0	0
T41	1479576	1479006	0	0
T72	920412	920288	0	0
T73	306132	305944	0	0
T74	445896	445692	0	0
T75	228304	228194	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678821586	5532	0	0
T145	168186	1839	0	0
T190	180156	0	0	0
T228	0	1847	0	0
T229	0	1846	0	0
T230	484762	0	0	0
T231	501954	0	0	0
T232	1380324	0	0	0
T233	512536	0	0	0
T234	162514	0	0	0
T235	256738	0	0	0
T236	448008	0	0	0
T237	412174	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T11,T12
0	1	Covered	T145,T228,T229
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T228,T229
1	Covered	T145,T11,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T228,T229
1	Covered	T145,T11,T12

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T228,T229
1	1	Covered	T145,T228,T229

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T11,T12
1	0	Covered	T145,T228,T229
1	1	Covered	T145,T228,T229

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T228,T229

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T11,T12
0	Covered	T145,T228,T229

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T11,T12
0	Covered	T145,T228,T229

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	339410793	330810988	0	0
CheckNGreaterZero_A	948	948	0	0
GntImpliesReady_A	339410793	4500	0	0
GntImpliesValid_A	339410793	4500	0	0
GrantKnown_A	339410793	330810988	0	0
IdxKnown_A	339410793	330810988	0	0
IndexIsCorrect_A	339410793	4500	0	0
NoReadyValidNoGrant_A	339410793	0	0	0
Priority_A	339410793	4500	0	0
ReadyAndValidImplyGrant_A	339410793	4500	0	0
ReqAndReadyImplyGrant_A	339410793	4500	0	0
ReqImpliesValid_A	339410793	4500	0	0
ValidKnown_A	339410793	330810988	0	0
gen_data_port_assertion.DataFlow_A	339410793	4500	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	4500	0	0
T145	84093	1495	0	0
T190	90078	0	0	0
T228	0	1503	0	0
T229	0	1502	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T11,T12
0	1	Covered	T145,T228,T229
1	0	Covered	T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T11,T228
1	Covered	T145,T11,T12

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T11,T228
1	Covered	T145,T11,T12

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T228,T229
1	1	Covered	T145,T11,T228

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T11,T12
1	0	Covered	T145,T11,T228
1	1	Covered	T145,T228,T229

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T11,T228

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T11,T12
0	Covered	T145,T11,T228

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T11,T12
0	Covered	T145,T11,T228

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	339410793	330810988	0	0
CheckNGreaterZero_A	948	948	0	0
GntImpliesReady_A	339410793	1032	0	0
GntImpliesValid_A	339410793	1032	0	0
GrantKnown_A	339410793	330810988	0	0
IdxKnown_A	339410793	330810988	0	0
IndexIsCorrect_A	339410793	1032	0	0
NoReadyValidNoGrant_A	339410793	0	0	0
Priority_A	339410793	1032	0	0
ReadyAndValidImplyGrant_A	339410793	1032	0	0
ReqAndReadyImplyGrant_A	339410793	1032	0	0
ReqImpliesValid_A	339410793	1032	0	0
ValidKnown_A	339410793	330810988	0	0
gen_data_port_assertion.DataFlow_A	339410793	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	330810988	0	0
T17	76680	76622	0	0
T18	154838	154783	0	0
T19	89980	89929	0	0
T20	237755	237642	0	0
T21	233791	233674	0	0
T41	739788	739503	0	0
T72	460206	460144	0	0
T73	153066	152972	0	0
T74	222948	222846	0	0
T75	114152	114097	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	1032	0	0
T145	84093	344	0	0
T190	90078	0	0	0
T228	0	344	0	0
T229	0	344	0	0
T230	242381	0	0	0
T231	250977	0	0	0
T232	690162	0	0	0
T233	256268	0	0	0
T234	81257	0	0	0
T235	128369	0	0	0
T236	224004	0	0	0
T237	206087	0	0	0