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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.41 95.44 94.71 95.74 95.42 97.57 99.57


Total test records in report: 2857
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T1116 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3307104687 Jan 25 12:30:11 AM PST 24 Jan 25 12:53:30 AM PST 24 6979267456 ps
T1117 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1642056173 Jan 25 03:59:21 AM PST 24 Jan 25 04:09:30 AM PST 24 5751457294 ps
T1118 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3023647825 Jan 25 01:52:22 AM PST 24 Jan 25 02:00:49 AM PST 24 3732325586 ps
T157 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2346268714 Jan 25 12:51:11 AM PST 24 Jan 25 01:01:31 AM PST 24 3735018923 ps
T169 /workspace/coverage/default/2.chip_sw_flash_init.835709354 Jan 25 03:38:45 AM PST 24 Jan 25 04:09:17 AM PST 24 15702744088 ps
T1119 /workspace/coverage/default/2.chip_sw_otbn_smoketest.4030440902 Jan 25 01:33:28 AM PST 24 Jan 25 02:11:43 AM PST 24 9545200508 ps
T133 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1263447652 Jan 25 12:10:56 AM PST 24 Jan 25 12:19:14 AM PST 24 3849149584 ps
T654 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3034239825 Jan 25 02:05:03 AM PST 24 Jan 25 02:13:04 AM PST 24 4204726740 ps
T1120 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.487381526 Jan 25 05:38:32 AM PST 24 Jan 25 05:51:54 AM PST 24 5531878130 ps
T317 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2198680940 Jan 25 03:39:29 AM PST 24 Jan 25 03:50:31 AM PST 24 5534706356 ps
T1121 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.165850602 Jan 25 03:03:45 AM PST 24 Jan 25 03:09:05 AM PST 24 3163548741 ps
T1122 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2232347153 Jan 25 01:33:28 AM PST 24 Jan 25 01:39:03 AM PST 24 3036450810 ps
T1123 /workspace/coverage/default/1.chip_sw_kmac_idle.828714389 Jan 25 12:33:38 AM PST 24 Jan 25 12:38:13 AM PST 24 2163851772 ps
T1124 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2940711763 Jan 25 04:32:16 AM PST 24 Jan 25 04:53:28 AM PST 24 5555573242 ps
T1125 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2971096325 Jan 24 11:56:40 PM PST 24 Jan 25 12:02:46 AM PST 24 3345398428 ps
T636 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2125997905 Jan 25 02:58:59 AM PST 24 Jan 25 03:05:06 AM PST 24 3430422920 ps
T1126 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4047277198 Jan 25 12:27:03 AM PST 24 Jan 25 01:02:23 AM PST 24 10770547315 ps
T1127 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.471815770 Jan 25 12:08:28 AM PST 24 Jan 25 12:17:34 AM PST 24 5544755236 ps
T1128 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3720348288 Jan 24 11:56:08 PM PST 24 Jan 25 12:15:16 AM PST 24 5437443937 ps
T1129 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.944196401 Jan 25 01:37:22 AM PST 24 Jan 25 02:21:12 AM PST 24 13008047140 ps
T1130 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2406686333 Jan 25 01:38:07 AM PST 24 Jan 25 02:03:06 AM PST 24 9758008365 ps
T1131 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1186941022 Jan 25 02:26:45 AM PST 24 Jan 25 02:43:22 AM PST 24 7102815196 ps
T1132 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1116458694 Jan 25 12:53:53 AM PST 24 Jan 25 01:01:26 AM PST 24 3212347732 ps
T194 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2180933198 Jan 25 01:16:24 AM PST 24 Jan 25 01:26:32 AM PST 24 5684151652 ps
T1133 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3999711206 Jan 25 12:21:08 AM PST 24 Jan 25 01:21:35 AM PST 24 11976395520 ps
T290 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.529975895 Jan 25 01:28:47 AM PST 24 Jan 25 01:46:52 AM PST 24 5010648365 ps
T1134 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3205609802 Jan 25 01:35:20 AM PST 24 Jan 25 01:50:48 AM PST 24 4405777656 ps
T224 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2149972930 Jan 25 01:48:26 AM PST 24 Jan 25 01:59:47 AM PST 24 5009189400 ps
T1135 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3559398790 Jan 25 12:26:09 AM PST 24 Jan 25 12:44:07 AM PST 24 7884510391 ps
T267 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3083927498 Jan 25 01:07:51 AM PST 24 Jan 25 01:29:35 AM PST 24 5840878958 ps
T1136 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2578815215 Jan 25 01:09:34 AM PST 24 Jan 25 01:20:15 AM PST 24 3540247112 ps
T1137 /workspace/coverage/default/1.chip_sw_aes_idle.302908147 Jan 25 01:47:55 AM PST 24 Jan 25 01:51:41 AM PST 24 2750102144 ps
T300 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4112634367 Jan 25 12:23:15 AM PST 24 Jan 25 12:40:27 AM PST 24 5123093538 ps
T1138 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3303876161 Jan 25 12:23:00 AM PST 24 Jan 25 12:40:18 AM PST 24 4645447410 ps
T676 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3894359526 Jan 25 02:05:04 AM PST 24 Jan 25 02:18:51 AM PST 24 4817245350 ps
T1139 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.936196885 Jan 25 02:09:39 AM PST 24 Jan 25 02:19:46 AM PST 24 5080136450 ps
T705 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2370166940 Jan 25 01:48:14 AM PST 24 Jan 25 01:57:54 AM PST 24 5437563740 ps
T1140 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2382227874 Jan 25 12:37:20 AM PST 24 Jan 25 12:49:38 AM PST 24 3531543008 ps
T709 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.588301891 Jan 25 02:01:52 AM PST 24 Jan 25 02:08:11 AM PST 24 3011975124 ps
T1141 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3496273597 Jan 25 12:03:27 AM PST 24 Jan 25 12:20:57 AM PST 24 5429841832 ps
T1142 /workspace/coverage/default/0.chip_sival_flash_info_access.246913220 Jan 24 11:52:43 PM PST 24 Jan 24 11:59:36 PM PST 24 4187245030 ps
T647 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.442606783 Jan 25 03:41:46 AM PST 24 Jan 25 03:47:22 AM PST 24 4153821152 ps
T1143 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.672846080 Jan 25 12:34:40 AM PST 24 Jan 25 01:19:31 AM PST 24 8450600702 ps
T1144 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3383669114 Jan 25 03:26:10 AM PST 24 Jan 25 03:37:34 AM PST 24 6270157052 ps
T1145 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2070568592 Jan 25 02:16:05 AM PST 24 Jan 25 02:25:52 AM PST 24 3527036160 ps
T43 /workspace/coverage/default/1.chip_tap_straps_rma.1428691387 Jan 25 01:15:24 AM PST 24 Jan 25 01:31:36 AM PST 24 7349809865 ps
T5 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.215637424 Jan 25 12:19:36 AM PST 24 Jan 25 12:27:03 AM PST 24 3081175720 ps
T1146 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.352519309 Jan 24 11:56:39 PM PST 24 Jan 25 12:10:45 AM PST 24 5049923060 ps
T1147 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.234685163 Jan 25 01:40:46 AM PST 24 Jan 25 01:51:41 AM PST 24 5586851862 ps
T336 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1355096496 Jan 25 12:51:49 AM PST 24 Jan 25 12:56:31 AM PST 24 2514796624 ps
T1148 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1671047568 Jan 25 12:35:44 AM PST 24 Jan 25 12:46:02 AM PST 24 4497034340 ps
T1149 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1913055171 Jan 25 01:42:03 AM PST 24 Jan 25 01:47:03 AM PST 24 2207020482 ps
T225 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122496866 Jan 25 01:55:59 AM PST 24 Jan 25 02:02:02 AM PST 24 4087438504 ps
T1150 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3570722484 Jan 25 02:23:13 AM PST 24 Jan 25 02:45:09 AM PST 24 11495444641 ps
T1151 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.512339319 Jan 25 02:08:24 AM PST 24 Jan 25 02:19:44 AM PST 24 5392352620 ps
T1152 /workspace/coverage/default/2.chip_tap_straps_prod.728612879 Jan 25 01:15:58 AM PST 24 Jan 25 01:19:26 AM PST 24 2738367812 ps
T1153 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3622887180 Jan 25 12:21:45 AM PST 24 Jan 25 12:27:19 AM PST 24 3245437647 ps
T1154 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1409587487 Jan 25 12:34:51 AM PST 24 Jan 25 12:46:09 AM PST 24 4942594893 ps
T1155 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1489377668 Jan 25 12:41:53 AM PST 24 Jan 25 12:54:31 AM PST 24 5035855703 ps
T1156 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1551302937 Jan 25 02:26:44 AM PST 24 Jan 25 02:34:31 AM PST 24 5984199733 ps
T1157 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3001970562 Jan 25 01:01:40 AM PST 24 Jan 25 01:14:13 AM PST 24 6514233878 ps
T1158 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2051626398 Jan 25 02:58:16 AM PST 24 Jan 25 03:09:30 AM PST 24 4933808530 ps
T1159 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3430368186 Jan 25 12:54:24 AM PST 24 Jan 25 01:00:44 AM PST 24 5448983500 ps
T1160 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1735131537 Jan 24 11:59:20 PM PST 24 Jan 25 12:03:59 AM PST 24 3097058420 ps
T1161 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3498961442 Jan 25 12:52:00 AM PST 24 Jan 25 12:58:25 AM PST 24 4088852368 ps
T581 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2775914263 Jan 25 12:39:53 AM PST 24 Jan 25 12:50:18 AM PST 24 5461833315 ps
T1162 /workspace/coverage/default/0.rom_e2e_shutdown_output.1869717821 Jan 25 05:53:34 AM PST 24 Jan 25 06:42:57 AM PST 24 25869018054 ps
T1163 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2243594392 Jan 25 12:54:43 AM PST 24 Jan 25 01:03:59 AM PST 24 9041759548 ps
T1164 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1064257064 Jan 25 12:08:49 AM PST 24 Jan 25 12:15:31 AM PST 24 3696547440 ps
T1165 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2850661840 Jan 25 01:02:20 AM PST 24 Jan 25 01:10:55 AM PST 24 5329729016 ps
T643 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2799807983 Jan 25 01:36:43 AM PST 24 Jan 25 01:48:17 AM PST 24 5013624388 ps
T1166 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3287927020 Jan 25 12:52:20 AM PST 24 Jan 25 01:12:09 AM PST 24 5947532607 ps
T1167 /workspace/coverage/default/67.chip_sw_all_escalation_resets.3140832638 Jan 25 01:57:19 AM PST 24 Jan 25 02:11:04 AM PST 24 6400752814 ps
T1168 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2905276610 Jan 25 01:17:53 AM PST 24 Jan 25 01:25:24 AM PST 24 4825219062 ps
T1169 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2588342847 Jan 25 12:00:15 AM PST 24 Jan 25 12:08:11 AM PST 24 5730072968 ps
T702 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2690022017 Jan 25 04:22:20 AM PST 24 Jan 25 04:28:21 AM PST 24 3716961318 ps
T618 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469460934 Jan 25 02:02:51 AM PST 24 Jan 25 02:11:33 AM PST 24 3952322172 ps
T44 /workspace/coverage/default/0.chip_tap_straps_rma.2049371422 Jan 25 12:28:15 AM PST 24 Jan 25 12:36:48 AM PST 24 5584373387 ps
T22 /workspace/coverage/default/2.chip_jtag_csr_rw.6364367 Jan 25 01:09:11 AM PST 24 Jan 25 01:29:02 AM PST 24 9737506062 ps
T1170 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1158928559 Jan 25 01:29:50 AM PST 24 Jan 25 01:51:16 AM PST 24 9878929706 ps
T1171 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1478507488 Jan 25 12:39:00 AM PST 24 Jan 25 12:47:01 AM PST 24 4757385400 ps
T1172 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.304018639 Jan 25 12:55:32 AM PST 24 Jan 25 01:22:40 AM PST 24 12151134201 ps
T1173 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1157780262 Jan 25 01:38:10 AM PST 24 Jan 25 01:51:28 AM PST 24 4859472918 ps
T685 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119511777 Jan 25 01:48:17 AM PST 24 Jan 25 01:55:34 AM PST 24 3788987668 ps
T349 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.275965538 Jan 25 12:37:49 AM PST 24 Jan 25 12:45:01 AM PST 24 4685720488 ps
T1174 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3831239768 Jan 24 11:57:47 PM PST 24 Jan 25 12:11:06 AM PST 24 4397735370 ps
T716 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1629196438 Jan 25 01:42:38 AM PST 24 Jan 25 01:51:24 AM PST 24 3861922612 ps
T1175 /workspace/coverage/default/1.chip_sw_example_flash.49408579 Jan 25 01:52:35 AM PST 24 Jan 25 01:56:42 AM PST 24 2610324912 ps
T1176 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3538982689 Jan 25 02:29:38 AM PST 24 Jan 25 02:34:05 AM PST 24 2957585665 ps
T698 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4118595098 Jan 25 02:02:24 AM PST 24 Jan 25 02:11:24 AM PST 24 3824442616 ps
T686 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1430653380 Jan 25 02:03:27 AM PST 24 Jan 25 02:16:36 AM PST 24 5284532542 ps
T1177 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3127534552 Jan 25 12:37:10 AM PST 24 Jan 25 12:48:01 AM PST 24 4544992418 ps
T166 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.13119920 Jan 25 01:08:43 AM PST 24 Jan 25 03:02:24 AM PST 24 19078617768 ps
T1178 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2124363955 Jan 25 01:15:44 AM PST 24 Jan 25 01:33:23 AM PST 24 7710272312 ps
T1179 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2883583549 Jan 25 02:09:46 AM PST 24 Jan 25 02:18:10 AM PST 24 4130590780 ps
T1180 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2580039950 Jan 25 12:07:39 AM PST 24 Jan 25 12:11:07 AM PST 24 2651908640 ps
T1181 /workspace/coverage/default/3.chip_tap_straps_dev.2408683786 Jan 25 01:34:35 AM PST 24 Jan 25 02:07:38 AM PST 24 14535336125 ps
T1182 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2668570169 Jan 25 12:55:02 AM PST 24 Jan 25 01:18:54 AM PST 24 8096114936 ps
T1183 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.491757119 Jan 25 01:39:30 AM PST 24 Jan 25 01:55:24 AM PST 24 4413337320 ps
T199 /workspace/coverage/default/48.chip_sw_all_escalation_resets.257206043 Jan 25 02:52:10 AM PST 24 Jan 25 03:01:29 AM PST 24 5739556882 ps
T1184 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2305823801 Jan 25 12:21:33 AM PST 24 Jan 25 01:22:41 AM PST 24 11986234040 ps
T1185 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2907625096 Jan 25 12:25:56 AM PST 24 Jan 25 12:31:22 AM PST 24 3694868390 ps
T677 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1905464400 Jan 25 01:44:47 AM PST 24 Jan 25 01:56:53 AM PST 24 5373473404 ps
T1186 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3628484595 Jan 25 12:46:01 AM PST 24 Jan 25 12:49:51 AM PST 24 2734090592 ps
T1187 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3049686423 Jan 25 12:00:23 AM PST 24 Jan 25 12:04:13 AM PST 24 2413688736 ps
T228 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3514630487 Jan 25 12:12:05 AM PST 24 Jan 25 12:16:23 AM PST 24 3259368620 ps
T1188 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.589590472 Jan 25 12:01:43 AM PST 24 Jan 25 12:08:57 AM PST 24 4279772504 ps
T1189 /workspace/coverage/default/4.chip_tap_straps_rma.2626044498 Jan 25 02:18:32 AM PST 24 Jan 25 02:25:18 AM PST 24 4194072464 ps
T1190 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3829102469 Jan 24 11:55:59 PM PST 24 Jan 25 12:13:47 AM PST 24 5722149776 ps
T1191 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3589027791 Jan 25 01:13:42 AM PST 24 Jan 25 01:23:03 AM PST 24 3947599128 ps
T650 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2666571040 Jan 25 02:35:37 AM PST 24 Jan 25 02:43:09 AM PST 24 4558104690 ps
T1192 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1740318439 Jan 25 12:22:22 AM PST 24 Jan 25 12:36:15 AM PST 24 5074253012 ps
T90 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1201923802 Jan 25 02:23:06 AM PST 24 Jan 25 03:31:57 AM PST 24 17918691480 ps
T1193 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2954603739 Jan 25 12:13:41 AM PST 24 Jan 25 12:17:55 AM PST 24 2353728803 ps
T662 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2758479024 Jan 25 01:37:07 AM PST 24 Jan 25 01:48:57 AM PST 24 4717079308 ps
T119 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2099734491 Jan 24 11:54:31 PM PST 24 Jan 25 12:04:09 AM PST 24 4330935372 ps
T291 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.457332990 Jan 25 01:31:35 AM PST 24 Jan 25 01:50:54 AM PST 24 6118741880 ps
T701 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.308639566 Jan 25 01:38:52 AM PST 24 Jan 25 01:46:26 AM PST 24 4047691960 ps
T1194 /workspace/coverage/default/1.rom_e2e_static_critical.113592541 Jan 25 03:26:12 AM PST 24 Jan 25 04:09:59 AM PST 24 10924483080 ps
T678 /workspace/coverage/default/27.chip_sw_all_escalation_resets.329248878 Jan 25 01:45:21 AM PST 24 Jan 25 02:00:00 AM PST 24 5248030144 ps
T1195 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3281253687 Jan 25 12:22:07 AM PST 24 Jan 25 01:05:38 AM PST 24 8607462702 ps
T1196 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.629682268 Jan 25 05:09:49 AM PST 24 Jan 25 05:15:10 AM PST 24 3562316045 ps
T1197 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.525278471 Jan 25 02:21:16 AM PST 24 Jan 25 02:25:18 AM PST 24 2903252210 ps
T1198 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1167029713 Jan 25 12:20:54 AM PST 24 Jan 25 01:12:19 AM PST 24 9936574300 ps
T1199 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1492078563 Jan 25 12:35:11 AM PST 24 Jan 25 12:42:32 AM PST 24 4793058728 ps
T1200 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3368001356 Jan 24 11:52:56 PM PST 24 Jan 25 12:04:23 AM PST 24 5229517380 ps
T1201 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1341948803 Jan 25 02:45:38 AM PST 24 Jan 25 04:14:29 AM PST 24 22950325960 ps
T1202 /workspace/coverage/default/2.rom_keymgr_functest.3696419715 Jan 25 01:32:09 AM PST 24 Jan 25 01:43:29 AM PST 24 4324039872 ps
T1203 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3869782058 Jan 25 01:12:56 AM PST 24 Jan 25 01:23:57 AM PST 24 3912735864 ps
T127 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1313826961 Jan 25 12:52:29 AM PST 24 Jan 25 12:56:53 AM PST 24 3094058028 ps
T1204 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3461673699 Jan 25 01:35:58 AM PST 24 Jan 25 01:42:54 AM PST 24 7592827710 ps
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T1207 /workspace/coverage/default/4.chip_tap_straps_testunlock0.3209593936 Jan 25 02:44:43 AM PST 24 Jan 25 02:47:18 AM PST 24 2760032186 ps
T1208 /workspace/coverage/default/4.chip_sw_uart_tx_rx.20658588 Jan 25 01:36:04 AM PST 24 Jan 25 01:54:10 AM PST 24 5517196568 ps
T1209 /workspace/coverage/default/4.chip_tap_straps_dev.556475255 Jan 25 01:36:05 AM PST 24 Jan 25 01:38:44 AM PST 24 2354379977 ps
T1210 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1497360483 Jan 25 12:03:50 AM PST 24 Jan 25 12:11:41 AM PST 24 4428229796 ps
T229 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1237229217 Jan 25 12:38:49 AM PST 24 Jan 25 12:44:22 AM PST 24 2939794588 ps
T1211 /workspace/coverage/default/2.chip_sw_kmac_idle.787467501 Jan 25 01:10:25 AM PST 24 Jan 25 01:14:28 AM PST 24 2683019740 ps
T1212 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1419578623 Jan 25 02:03:19 AM PST 24 Jan 25 02:14:30 AM PST 24 5152515109 ps
T1213 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3203022341 Jan 25 03:04:53 AM PST 24 Jan 25 03:09:41 AM PST 24 3153779640 ps
T680 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1440613243 Jan 25 01:47:25 AM PST 24 Jan 25 01:54:09 AM PST 24 4006659360 ps
T1214 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1732451331 Jan 25 01:37:32 AM PST 24 Jan 25 01:44:06 AM PST 24 3675618846 ps
T1215 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1622073552 Jan 25 08:26:41 AM PST 24 Jan 25 08:38:02 AM PST 24 5317488738 ps
T1216 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.299630647 Jan 25 12:49:44 AM PST 24 Jan 25 01:09:37 AM PST 24 6102836916 ps
T1217 /workspace/coverage/default/66.chip_sw_all_escalation_resets.4054780076 Jan 25 01:58:13 AM PST 24 Jan 25 02:10:11 AM PST 24 4825999890 ps
T1218 /workspace/coverage/default/2.chip_tap_straps_rma.3185087441 Jan 25 01:41:53 AM PST 24 Jan 25 01:46:33 AM PST 24 3717465388 ps
T16 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2326166408 Jan 25 02:35:00 AM PST 24 Jan 25 02:40:19 AM PST 24 3781206952 ps
T1219 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3789566170 Jan 25 02:24:57 AM PST 24 Jan 25 02:31:37 AM PST 24 4657391676 ps
T318 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3005093125 Jan 25 01:55:30 AM PST 24 Jan 25 02:02:09 AM PST 24 4002831290 ps
T1220 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3860908189 Jan 25 12:20:35 AM PST 24 Jan 25 12:25:36 AM PST 24 3330854540 ps
T713 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3819748197 Jan 25 01:56:20 AM PST 24 Jan 25 02:08:06 AM PST 24 5902022694 ps
T1221 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4276284276 Jan 25 01:32:19 AM PST 24 Jan 25 01:37:59 AM PST 24 3616132690 ps
T238 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1996639378 Jan 25 12:34:27 AM PST 24 Jan 25 12:50:08 AM PST 24 9905607417 ps
T206 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1823972678 Jan 25 01:35:25 AM PST 24 Jan 25 01:50:07 AM PST 24 5444965220 ps
T1222 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2369205179 Jan 25 02:03:08 AM PST 24 Jan 25 03:43:13 AM PST 24 23081551439 ps
T1223 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.54863832 Jan 25 01:46:02 AM PST 24 Jan 25 01:53:41 AM PST 24 4042497760 ps
T1224 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3913850884 Jan 25 12:56:14 AM PST 24 Jan 25 01:26:20 AM PST 24 7206673409 ps
T1225 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2362483153 Jan 25 12:20:54 AM PST 24 Jan 25 12:34:02 AM PST 24 5835376750 ps
T1226 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1231696958 Jan 25 01:41:38 AM PST 24 Jan 25 02:01:18 AM PST 24 5114996568 ps
T1227 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.74145452 Jan 25 04:03:12 AM PST 24 Jan 25 04:12:32 AM PST 24 3984681610 ps
T1228 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1960850314 Jan 25 12:05:39 AM PST 24 Jan 25 12:10:03 AM PST 24 2589503272 ps
T1229 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1556622640 Jan 25 01:02:49 AM PST 24 Jan 25 01:08:21 AM PST 24 3510756760 ps
T1230 /workspace/coverage/default/2.chip_sw_example_concurrency.2781939794 Jan 25 12:46:21 AM PST 24 Jan 25 12:50:34 AM PST 24 3211972358 ps
T1231 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3272447505 Jan 25 12:05:37 AM PST 24 Jan 25 12:10:41 AM PST 24 3004855972 ps
T1232 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.7035174 Jan 25 02:00:39 AM PST 24 Jan 25 02:27:03 AM PST 24 23511720660 ps
T350 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1023130626 Jan 25 12:10:58 AM PST 24 Jan 25 12:17:59 AM PST 24 3406150596 ps
T1233 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4021311936 Jan 25 06:20:03 AM PST 24 Jan 25 06:32:13 AM PST 24 8244687604 ps
T1234 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3248332628 Jan 24 11:55:59 PM PST 24 Jan 25 12:10:36 AM PST 24 4583432715 ps
T639 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3784810788 Jan 25 02:03:57 AM PST 24 Jan 25 02:15:17 AM PST 24 5676353774 ps
T703 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.4161282042 Jan 25 06:17:31 AM PST 24 Jan 25 06:24:00 AM PST 24 3851691140 ps
T1235 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.4206648771 Jan 25 12:50:27 AM PST 24 Jan 25 05:12:05 AM PST 24 65433984567 ps
T1236 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2215065916 Jan 25 02:19:49 AM PST 24 Jan 25 02:26:06 AM PST 24 3742745822 ps
T1237 /workspace/coverage/default/2.chip_sw_power_idle_load.571193039 Jan 25 04:04:55 AM PST 24 Jan 25 04:16:24 AM PST 24 4073136916 ps
T1238 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.608451272 Jan 25 01:57:12 AM PST 24 Jan 25 02:07:49 AM PST 24 4901483880 ps
T1239 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2902765628 Jan 25 03:43:26 AM PST 24 Jan 25 03:46:28 AM PST 24 2547518056 ps
T1240 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3096000484 Jan 25 02:09:03 AM PST 24 Jan 25 02:30:39 AM PST 24 6164702556 ps
T1241 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1148285318 Jan 25 12:01:24 AM PST 24 Jan 25 12:09:03 AM PST 24 7271103264 ps
T110 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1292547408 Jan 25 01:10:21 AM PST 24 Jan 25 01:18:25 AM PST 24 5132070048 ps
T1242 /workspace/coverage/default/2.chip_sw_aes_idle.3439459786 Jan 25 01:04:19 AM PST 24 Jan 25 01:08:10 AM PST 24 2181936736 ps
T266 /workspace/coverage/default/2.chip_plic_all_irqs_0.1113884518 Jan 25 02:57:58 AM PST 24 Jan 25 03:16:49 AM PST 24 5768145336 ps
T126 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1450117290 Jan 25 01:29:12 AM PST 24 Jan 25 01:34:11 AM PST 24 3439318654 ps
T24 /workspace/coverage/default/1.chip_sw_alert_test.1460123590 Jan 25 12:29:16 AM PST 24 Jan 25 12:34:16 AM PST 24 3728032740 ps
T1243 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1945961549 Jan 25 12:26:48 AM PST 24 Jan 25 01:37:35 AM PST 24 20535464400 ps
T1244 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1554654669 Jan 25 03:59:21 AM PST 24 Jan 25 04:04:59 AM PST 24 3809283964 ps
T1245 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.444874294 Jan 25 12:37:13 AM PST 24 Jan 25 12:48:45 AM PST 24 4465843176 ps
T171 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3585362062 Jan 25 12:40:44 AM PST 24 Jan 25 01:14:50 AM PST 24 18909158945 ps
T1246 /workspace/coverage/default/80.chip_sw_all_escalation_resets.3855036576 Jan 25 02:02:12 AM PST 24 Jan 25 02:15:25 AM PST 24 4974845320 ps
T1247 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3070235945 Jan 25 12:32:57 AM PST 24 Jan 25 12:41:10 AM PST 24 3864196142 ps
T1248 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.331086035 Jan 25 12:01:41 AM PST 24 Jan 25 12:07:14 AM PST 24 3458188071 ps
T1249 /workspace/coverage/default/1.chip_sw_gpio_smoketest.1799059496 Jan 25 12:46:10 AM PST 24 Jan 25 12:52:23 AM PST 24 3046780294 ps
T1250 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3080276434 Jan 25 12:50:14 AM PST 24 Jan 25 01:09:37 AM PST 24 5697135377 ps
T298 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.525689801 Jan 25 12:01:50 AM PST 24 Jan 25 12:11:52 AM PST 24 4020023684 ps
T1251 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2523975279 Jan 25 01:40:34 AM PST 24 Jan 25 03:17:41 AM PST 24 22746410100 ps
T1252 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.265389466 Jan 25 12:36:45 AM PST 24 Jan 25 12:41:42 AM PST 24 2463639848 ps
T727 /workspace/coverage/default/85.chip_sw_all_escalation_resets.924870923 Jan 25 02:02:54 AM PST 24 Jan 25 02:14:38 AM PST 24 4326623960 ps
T123 /workspace/coverage/default/1.chip_plic_all_irqs_10.2797366577 Jan 25 12:35:06 AM PST 24 Jan 25 12:43:52 AM PST 24 4060628910 ps
T1253 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2540731568 Jan 25 01:26:56 AM PST 24 Jan 25 01:50:54 AM PST 24 6839830332 ps
T88 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.315363332 Jan 25 12:02:12 AM PST 24 Jan 25 12:13:13 AM PST 24 18803083724 ps
T687 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3795250900 Jan 25 03:42:52 AM PST 24 Jan 25 03:54:39 AM PST 24 5903704672 ps
T6 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2300893552 Jan 25 12:46:28 AM PST 24 Jan 25 12:51:57 AM PST 24 3207736754 ps
T1254 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.605086298 Jan 25 02:25:46 AM PST 24 Jan 25 02:38:14 AM PST 24 4483174128 ps
T1255 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3956698082 Jan 25 03:16:02 AM PST 24 Jan 25 03:28:29 AM PST 24 4005671176 ps
T25 /workspace/coverage/default/2.chip_sw_alert_test.862107013 Jan 25 06:29:16 AM PST 24 Jan 25 06:33:18 AM PST 24 3034281376 ps
T1256 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.363352615 Jan 25 01:37:39 AM PST 24 Jan 25 01:55:23 AM PST 24 11042387917 ps
T651 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1511457279 Jan 25 01:51:55 AM PST 24 Jan 25 01:58:37 AM PST 24 2852397064 ps
T1257 /workspace/coverage/default/2.chip_sw_aes_enc.758198151 Jan 25 01:04:47 AM PST 24 Jan 25 01:10:24 AM PST 24 3069160986 ps
T1258 /workspace/coverage/default/1.chip_sw_edn_kat.4274556910 Jan 25 06:17:08 AM PST 24 Jan 25 06:26:44 AM PST 24 3461843320 ps
T615 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1308687715 Jan 25 02:40:12 AM PST 24 Jan 25 02:46:00 AM PST 24 3630536814 ps
T1259 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.103554191 Jan 25 01:08:15 AM PST 24 Jan 25 01:14:03 AM PST 24 2845769576 ps
T1260 /workspace/coverage/default/0.chip_sw_otbn_randomness.2039380716 Jan 25 12:02:57 AM PST 24 Jan 25 12:22:08 AM PST 24 5958754660 ps
T1261 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.313431843 Jan 25 12:40:19 AM PST 24 Jan 25 12:46:05 AM PST 24 2916961876 ps
T91 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.710779715 Jan 25 12:13:30 AM PST 24 Jan 25 01:30:33 AM PST 24 20142711249 ps
T1262 /workspace/coverage/default/78.chip_sw_all_escalation_resets.2234569492 Jan 25 02:00:32 AM PST 24 Jan 25 02:12:02 AM PST 24 4294096472 ps
T1263 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2440900478 Jan 25 04:46:01 AM PST 24 Jan 25 04:50:16 AM PST 24 2680235112 ps
T1264 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3936593370 Jan 25 12:23:57 AM PST 24 Jan 25 12:27:44 AM PST 24 2191007374 ps
T1265 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2639444541 Jan 24 11:54:29 PM PST 24 Jan 25 12:55:13 AM PST 24 13793696126 ps
T1266 /workspace/coverage/default/0.rom_keymgr_functest.1737680824 Jan 25 12:19:53 AM PST 24 Jan 25 12:30:50 AM PST 24 5076589092 ps
T1267 /workspace/coverage/default/1.chip_sw_example_rom.1120107242 Jan 25 12:20:03 AM PST 24 Jan 25 12:22:12 AM PST 24 2809890688 ps
T1268 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2764387661 Jan 25 12:21:46 AM PST 24 Jan 25 01:22:03 AM PST 24 11122307457 ps
T1269 /workspace/coverage/default/2.rom_volatile_raw_unlock.1186830742 Jan 25 01:33:05 AM PST 24 Jan 25 02:07:21 AM PST 24 8832176278 ps
T1270 /workspace/coverage/default/2.rom_e2e_shutdown_output.1699188795 Jan 25 01:34:52 AM PST 24 Jan 25 02:37:54 AM PST 24 28094370828 ps
T174 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2796353879 Jan 25 02:51:12 AM PST 24 Jan 25 02:58:29 AM PST 24 4517142390 ps
T1271 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3437358952 Jan 25 12:26:37 AM PST 24 Jan 25 12:52:55 AM PST 24 13696086587 ps
T1272 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1133561266 Jan 25 01:08:45 AM PST 24 Jan 25 01:16:54 AM PST 24 3424595101 ps
T710 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1653077717 Jan 25 02:17:52 AM PST 24 Jan 25 02:23:59 AM PST 24 3794855400 ps
T1273 /workspace/coverage/default/0.chip_sw_flash_crash_alert.4078373755 Jan 25 04:18:57 AM PST 24 Jan 25 04:29:05 AM PST 24 4776002328 ps
T1274 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.678798531 Jan 25 12:49:34 AM PST 24 Jan 25 01:09:26 AM PST 24 5926146032 ps
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T308 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2658844311 Jan 25 01:17:36 AM PST 24 Jan 25 01:27:44 AM PST 24 2845340454 ps
T309 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2494906951 Jan 25 01:47:13 AM PST 24 Jan 25 01:56:23 AM PST 24 3378033864 ps
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T312 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.385320343 Jan 25 02:33:58 AM PST 24 Jan 25 02:39:23 AM PST 24 3632932501 ps
T313 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1436704601 Jan 25 02:01:39 AM PST 24 Jan 25 02:12:19 AM PST 24 5611925490 ps
T1275 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.287148175 Jan 25 01:13:15 AM PST 24 Jan 25 01:19:34 AM PST 24 3955603440 ps
T276 /workspace/coverage/default/1.chip_plic_all_irqs_20.4101275827 Jan 25 12:35:07 AM PST 24 Jan 25 12:49:04 AM PST 24 4725648024 ps
T649 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2012877914 Jan 25 01:54:42 AM PST 24 Jan 25 02:07:30 AM PST 24 6510459340 ps
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T1276 /workspace/coverage/default/2.chip_sival_flash_info_access.3622762993 Jan 25 12:46:14 AM PST 24 Jan 25 12:55:36 AM PST 24 3964987622 ps
T1277 /workspace/coverage/default/21.chip_sw_all_escalation_resets.4279726230 Jan 25 01:43:06 AM PST 24 Jan 25 01:57:32 AM PST 24 5759264834 ps
T1278 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001412086 Jan 25 01:42:46 AM PST 24 Jan 25 01:50:26 AM PST 24 4128468232 ps
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T1279 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2436872238 Jan 25 12:35:13 AM PST 24 Jan 25 12:59:39 AM PST 24 11631181460 ps
T1280 /workspace/coverage/default/2.chip_jtag_mem_access.2922218064 Jan 25 01:09:06 AM PST 24 Jan 25 01:34:06 AM PST 24 13480446963 ps
T1281 /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.2127238223 Jan 25 03:13:15 AM PST 24 Jan 25 03:14:46 AM PST 24 4837277120 ps
T755 /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.3597281725 Jan 25 03:35:04 AM PST 24 Jan 25 03:37:38 AM PST 24 9423605535 ps
T514 /workspace/coverage/cover_reg_top/0.xbar_stress_all.3595034210 Jan 25 02:48:16 AM PST 24 Jan 25 02:48:25 AM PST 24 70324716 ps
T1282 /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3003620108 Jan 25 03:10:56 AM PST 24 Jan 25 03:12:31 AM PST 24 4836456259 ps
T1283 /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1972870487 Jan 25 03:41:25 AM PST 24 Jan 25 03:41:33 AM PST 24 41354871 ps
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