Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1651131	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25731835

1

T1

12976

T2

10460

T3

7068

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17813298	1			T1	9442		T2	2402		T3	1770
values[0x0]	7917528	1			T1	3534		T2	8058		T3	5298
values[0x1]	1652140	1			T1	118		T2	290		T3	233

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27374581

1

T1

13094

T2

10750

T3

7301

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13678452	1			T1	6547		T2	5375		T3	3651
valid_sources[0x01]	13677634	1			T1	6547		T2	5375		T3	3650
valid_sources[0x02]	305	1			T14	34		T20	27		T23	28
valid_sources[0x03]	294	1			T14	67		T20	53		T23	30
valid_sources[0x04]	312	1			T14	34		T20	53		T23	48
valid_sources[0x05]	288	1			T14	32		T20	70		T23	40
valid_sources[0x06]	285	1			T14	2		T20	50		T23	60
valid_sources[0x07]	461	1			T14	54		T15	149		T20	55
valid_sources[0x08]	304	1			T14	46		T20	48		T23	59
valid_sources[0x09]	315	1			T14	104		T20	34		T23	27
valid_sources[0x0a]	251	1			T14	26		T20	38		T23	42
valid_sources[0x0b]	222	1			T14	17		T20	22		T23	48
valid_sources[0x0c]	2868	1			T14	7		T20	40		T23	42
valid_sources[0x0d]	283	1			T14	14		T15	16		T20	31
valid_sources[0x0e]	265	1			T20	42		T23	53		T195	57
valid_sources[0x0f]	440	1			T20	44		T23	45		T195	58
valid_sources[0x10]	473	1			T14	24		T20	69		T23	58
valid_sources[0x11]	290	1			T14	61		T20	32		T23	53
valid_sources[0x12]	306	1			T14	16		T20	30		T23	69
valid_sources[0x13]	259	1			T14	29		T20	37		T23	36
valid_sources[0x14]	1427	1			T14	34		T20	38		T23	40
valid_sources[0x15]	517	1			T14	99		T20	13		T23	54
valid_sources[0x16]	285	1			T14	36		T15	16		T20	11
valid_sources[0x17]	214	1			T20	24		T23	31		T195	61
valid_sources[0x18]	332	1			T14	16		T20	22		T23	38
valid_sources[0x19]	334	1			T14	49		T20	38		T23	59
valid_sources[0x1a]	312	1			T14	57		T20	38		T23	53
valid_sources[0x1b]	245	1			T14	20		T20	7		T23	49
valid_sources[0x1c]	310	1			T15	16		T20	69		T23	45
valid_sources[0x1d]	250	1			T14	11		T20	25		T23	47
valid_sources[0x1e]	275	1			T14	14		T20	48		T23	39
valid_sources[0x1f]	491	1			T14	30		T20	29		T23	40
valid_sources[0x20]	236	1			T14	23		T20	47		T23	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17813298

1

T1

9442

T2

2402

T3

1770

values[0x0]

all_enables

biggest_size

7913222

1

T1

3534

T2

8058

T3

5298

values[0x1]

all_enables

biggest_size

5315

1

T14

505

T15

416

T20

435