Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.85			90.85

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	90.74			90.74
tb.dut.top_earlgrey.u_i2c1	90.80			90.80
tb.dut.top_earlgrey.u_i2c2	90.80			90.80

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.80			90.80

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.80			90.80

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.80			90.80

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.80			90.80

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	328	298	90.85
Total Bits 0->1	164	149	90.85
Total Bits 1->0	164	149	90.85

Ports	48	40	83.33
Port Bits	328	298	90.85
Port Bits 0->1	164	149	90.85
Port Bits 1->0	164	149	90.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T74,T211,T131	Yes	T74,T211,T131	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T74,T211,T131	Yes	T74,T211,T131	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T74,T211,T53	Yes	T74,T211,T53	INPUT
tl_o.a_ready	Yes	Yes	T74,T211,T53	Yes	T74,T211,T53	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T74,T211,T131	Yes	T74,T211,T131	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T74,T211,T92	Yes	T74,T211,T53	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T220,T131	Yes	T74,T211,T53	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T74,T211,T92	Yes	T74,T211,T53	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T149,*T52,*T74	Yes	T149,T52,T74	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T220,T131	Yes	T74,T211,T53	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T74,*T211,*T131	Yes	T74,T211,T131	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T74,T211,T53	Yes	T74,T211,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T63,T36,T53	Yes	T63,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T63,T36,T53	Yes	T63,T36,T53	OUTPUT
cio_scl_i	Yes	Yes	T74,T211,T14	Yes	T74,T211,T14	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T74,T211,T319	Yes	T74,T211,T319	OUTPUT
cio_sda_i	Yes	Yes	T74,T211,T14	Yes	T74,T211,T14	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T74,T211,T319	Yes	T74,T211,T319	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T74,T211,T319	Yes	T74,T211,T319	OUTPUT
intr_rx_threshold_o	Yes	Yes	T74,T211,T319	Yes	T74,T211,T319	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_rx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_nak_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_scl_interference_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_interference_o	Yes	Yes	T204,T205,T149	Yes	T204,T205,T149	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_unstable_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_cmd_complete_o	Yes	Yes	T74,T211,T319	Yes	T74,T211,T319	OUTPUT
intr_tx_stretch_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_tx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_acq_full_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_unexp_stop_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_host_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	324	294	90.74
Total Bits 0->1	162	147	90.74
Total Bits 1->0	162	147	90.74

Ports	48	40	83.33
Port Bits	324	294	90.74
Port Bits 0->1	162	147	90.74
Port Bits 1->0	162	147	90.74

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T211,T131,T316	Yes	T211,T131,T316	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T211,T131,T316	Yes	T211,T131,T316	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T211,T53,T92	Yes	T211,T53,T92	INPUT
tl_o.a_ready	Yes	Yes	T211,T53,T92	Yes	T211,T53,T92	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T211,T316,T204	Yes	T211,T316,T204	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T211,T92,T220	Yes	T211,T53,T92	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T220,T131	Yes	T211,T53,T92	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T211,T92,T220	Yes	T211,T53,T92	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T149,*T52,*T211	Yes	T149,T52,T211	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T220,T131	Yes	T211,T53,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T211,*T131,*T316	Yes	T211,T131,T316	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T211,T53,T92	Yes	T211,T53,T92	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T63,T36,T53	Yes	T63,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T63,T36,T53	Yes	T63,T36,T53	OUTPUT
cio_scl_i	Yes	Yes	T211,T14,T15	Yes	T211,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T211,T316,T336	Yes	T211,T316,T336	OUTPUT
cio_sda_i	Yes	Yes	T211,T14,T15	Yes	T211,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T211,T316,T336	Yes	T211,T316,T336	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T211,T316,T204	Yes	T211,T316,T204	OUTPUT
intr_rx_threshold_o	Yes	Yes	T211,T316,T204	Yes	T211,T316,T204	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_rx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_nak_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_scl_interference_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_interference_o	Yes	Yes	T204,T205,T149	Yes	T204,T205,T149	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_unstable_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_cmd_complete_o	Yes	Yes	T211,T316,T204	Yes	T211,T316,T204	OUTPUT
intr_tx_stretch_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_tx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_acq_full_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_unexp_stop_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_host_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	326	296	90.80
Total Bits 0->1	163	148	90.80
Total Bits 1->0	163	148	90.80

Ports	48	40	83.33
Port Bits	326	296	90.80
Port Bits 0->1	163	148	90.80
Port Bits 1->0	163	148	90.80

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T131,T317,T318	Yes	T131,T317,T318	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T131,T317,T318	Yes	T131,T317,T318	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T53,T92,T220	Yes	T53,T92,T220	INPUT
tl_o.a_ready	Yes	Yes	T53,T92,T220	Yes	T53,T92,T220	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T131,T317,T318	Yes	T131,T317,T318	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T92,T220,T131	Yes	T53,T92,T220	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T220,T131	Yes	T53,T92,T220	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T92,T220,T131	Yes	T53,T92,T220	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T149,*T52,*T92	Yes	T149,T52,T92	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T220,T131	Yes	T53,T92,T220	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T131,*T317,*T318	Yes	T131,T317,T318	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T53,T92,T220	Yes	T53,T92,T220	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T36,T53,T92	Yes	T36,T53,T92	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T36,T53,T92	Yes	T36,T53,T92	OUTPUT
cio_scl_i	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T337,T149,T338	Yes	T337,T149,T338	OUTPUT
cio_sda_i	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T317,T337,T149	Yes	T317,T337,T149	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T337,T204,T205	Yes	T337,T204,T205	OUTPUT
intr_rx_threshold_o	Yes	Yes	T337,T204,T205	Yes	T337,T204,T205	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_rx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_nak_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_scl_interference_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_interference_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_unstable_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_cmd_complete_o	Yes	Yes	T317,T337,T204	Yes	T317,T337,T204	OUTPUT
intr_tx_stretch_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_tx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_acq_full_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_unexp_stop_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_host_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	326	296	90.80
Total Bits 0->1	163	148	90.80
Total Bits 1->0	163	148	90.80

Ports	48	40	83.33
Port Bits	326	296	90.80
Port Bits 0->1	163	148	90.80
Port Bits 1->0	163	148	90.80

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T74,T131,T319	Yes	T74,T131,T319	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T74,T131,T319	Yes	T74,T131,T319	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T74,T53,T92	Yes	T74,T53,T92	INPUT
tl_o.a_ready	Yes	Yes	T74,T53,T92	Yes	T74,T53,T92	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T74,T319,T204	Yes	T74,T319,T204	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T74,T92,T220	Yes	T74,T53,T92	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T220,T131	Yes	T74,T53,T92	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T74,T92,T220	Yes	T74,T53,T92	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T149,*T52,*T74	Yes	T149,T52,T74	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T220,T131	Yes	T74,T53,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T74,*T131,*T319	Yes	T74,T131,T319	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T74,T53,T92	Yes	T74,T53,T92	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T36,T53,T92	Yes	T36,T53,T92	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T36,T53,T92	Yes	T36,T53,T92	OUTPUT
cio_scl_i	Yes	Yes	T74,T14,T15	Yes	T74,T14,T15	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T74,T319,T339	Yes	T74,T319,T339	OUTPUT
cio_sda_i	Yes	Yes	T74,T14,T15	Yes	T74,T14,T15	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T74,T319,T339	Yes	T74,T319,T339	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T74,T319,T204	Yes	T74,T319,T204	OUTPUT
intr_rx_threshold_o	Yes	Yes	T74,T319,T204	Yes	T74,T319,T204	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_rx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_nak_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_scl_interference_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_interference_o	Yes	Yes	T204,T205,T149	Yes	T204,T205,T149	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_sda_unstable_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_cmd_complete_o	Yes	Yes	T74,T319,T204	Yes	T74,T319,T204	OUTPUT
intr_tx_stretch_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_tx_overflow_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_acq_full_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_unexp_stop_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT
intr_host_timeout_o	Yes	Yes	T204,T205,T206	Yes	T204,T205,T206	OUTPUT

*Tests covering at least one bit in the range