Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.95			80.95

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_device	90.43			90.43

---

Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.43			90.43

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.43			90.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	59	40	67.80
Total Bits	420	340	80.95
Total Bits 0->1	210	170	80.95
Total Bits 1->0	210	170	80.95

Ports	59	40	67.80
Port Bits	420	340	80.95
Port Bits 0->1	210	170	80.95
Port Bits 1->0	210	170	80.95

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[12:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T10,T53,T12	Yes	T10,T53,T12	INPUT
tl_o.a_ready	Yes	Yes	T10,T53,T12	Yes	T10,T53,T12	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T10,T131,T132	Yes	T10,T53,T12	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T53,T12	Yes	T10,T12,T24	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T10,*T12	Yes	T51,T10,T53	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T10,T131,T132	Yes	T10,T53,T12	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T10,*T53,*T12	Yes	T10,T12,T24	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T10,T53,T12	Yes	T10,T53,T12	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T21,T36,T53	Yes	T21,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T21,T36,T53	Yes	T21,T36,T53	OUTPUT
cio_sck_i	Yes	Yes	T10,T12,T24	Yes	T10,T7,T12	INPUT
cio_csb_i	Yes	Yes	T10,T7,T12	Yes	T10,T7,T12	INPUT
cio_sd_o[3:0]	Yes	Yes	T10,T12,T132	Yes	T10,T12,T132	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T10,T12,T132	Yes	T10,T12,T132	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
cio_tpm_csb_i	Yes	Yes	T24,T14,T15	Yes	T24,T14,T15	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T10,*T12,*T132	Yes	T10,T12,T132	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T10,T7,T12	Yes	T10,T7,T12	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T10,T132,T134	Yes	T10,T12,T132	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T10,T135,T132	Yes	T10,T135,T132	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T24,T135,T136	Yes	T24,T135,T136	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
sck_monitor_o	Yes	Yes	T10,T12,T24	Yes	T10,T7,T12	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device

	Total	Covered	Percent
Totals	49	40	81.63
Total Bits	376	340	90.43
Total Bits 0->1	188	170	90.43
Total Bits 1->0	188	170	90.43

Ports	49	40	81.63
Port Bits	376	340	90.43
Port Bits 0->1	188	170	90.43
Port Bits 1->0	188	170	90.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[12:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T10,T53,T12	Yes	T10,T53,T12	INPUT
tl_o.a_ready	Yes	Yes	T10,T53,T12	Yes	T10,T53,T12	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T10,T131,T132	Yes	T10,T53,T12	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T53,T12	Yes	T10,T12,T24	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T10,*T12	Yes	T51,T10,T53	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T10,T131,T132	Yes	T10,T53,T12	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T10,*T53,*T12	Yes	T10,T12,T24	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T10,T53,T12	Yes	T10,T53,T12	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T21,T36,T53	Yes	T21,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T133,T37	Yes	T36,T133,T37	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T21,T36,T53	Yes	T21,T36,T53	OUTPUT
cio_sck_i	Yes	Yes	T10,T12,T24	Yes	T10,T7,T12	INPUT
cio_csb_i	Yes	Yes	T10,T7,T12	Yes	T10,T7,T12	INPUT
cio_sd_o[3:0]	Yes	Yes	T10,T12,T132	Yes	T10,T12,T132	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T10,T12,T132	Yes	T10,T12,T132	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
cio_tpm_csb_i	Yes	Yes	T24,T14,T15	Yes	T24,T14,T15	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T10,*T12,*T132	Yes	T10,T12,T132	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
passthrough_o.csb_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.csb	Yes	Yes	T10,T7,T12	Yes	T10,T7,T12	OUTPUT
passthrough_o.sck_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.sck	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T10,T132,T134	Yes	T10,T12,T132	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T10,T135,T132	Yes	T10,T135,T132	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T24,T135,T136	Yes	T24,T135,T136	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sck_monitor_o	Yes	Yes	T10,T12,T24	Yes	T10,T7,T12	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range