Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.36			84.36

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host1	83.33			83.33
tb.dut.top_earlgrey.u_spi_host0	84.66			84.66

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33			83.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33			83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.66			84.66

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.66			84.66

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	32	69.57
Total Bits	358	302	84.36
Total Bits 0->1	179	151	84.36
Total Bits 1->0	179	151	84.36

Ports	46	32	69.57
Port Bits	358	302	84.36
Port Bits 0->1	179	151	84.36
Port Bits 1->0	179	151	84.36

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T75,*T10,*T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T75,*T22,*T53	Yes	T75,T22,T53	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T75,*T10,*T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T51,*T75,*T10	Yes	T51,T75,T10	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T132,*T134	Yes	T10,T132,T134	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_valid	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_o.a_ready	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T75,*T10	Yes	T51,T75,T10	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T75,*T10,*T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T196,T36,T53	Yes	T196,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T196,T36,T133	Yes	T196,T36,T133	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T196,T36,T133	Yes	T196,T36,T133	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T196,T36,T53	Yes	T196,T36,T53	OUTPUT
cio_sck_o	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	OUTPUT
cio_sck_en_o	Yes	Yes	T10,T12,T132	Yes	T10,T11,T22	OUTPUT
cio_csb_o	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	OUTPUT
cio_csb_en_o	Yes	Yes	T10,T12,T132	Yes	T10,T11,T22	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T10,*T11,*T22	Yes	T10,T11,T22	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T10,*T12,*T132	Yes	T10,T12,T132	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T10,T7,T12	Yes	T10,T7,T12	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
passthrough_i.passthrough_en	Yes	Yes	T10,T132,T134	Yes	T10,T12,T132	INPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T11,T22	Yes	T10,T11,T22	OUTPUT
intr_error_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_spi_event_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	26	68.42
Total Bits	324	270	83.33
Total Bits 0->1	162	135	83.33
Total Bits 1->0	162	135	83.33

Ports	38	26	68.42
Port Bits	324	270	83.33
Port Bits 0->1	162	135	83.33
Port Bits 1->0	162	135	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T22,T53,T135	Yes	T22,T53,T135	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T75,*T22,*T53	Yes	T75,T22,T53	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T22,T53,T135	Yes	T22,T53,T135	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T75,T22,*T53	Yes	T75,T22,T53	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T75,*T22,*T53	Yes	T75,T22,T53	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T75,*T22,*T53	Yes	T75,T22,T53	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T51,*T75,*T22	Yes	T51,T75,T22	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T75,T22,T147	Yes	T75,T22,T147	INPUT
tl_i.a_valid	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	INPUT
tl_o.a_ready	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T22,T135,T131	Yes	T22,T135,T131	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T22,T147	Yes	T75,T22,T53	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T75,T22,T147	Yes	T75,T22,T53	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T22,T135,T131	Yes	T22,T135,T131	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T75,*T22	Yes	T51,T75,T22	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T75,T22,T147	Yes	T75,T22,T53	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T75,*T22,*T147	Yes	T75,T22,T147	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T75,T22,T53	Yes	T75,T22,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T196,T36,T53	Yes	T196,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T196,T36,T133	Yes	T196,T36,T133	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T196,T36,T133	Yes	T196,T36,T133	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T196,T36,T53	Yes	T196,T36,T53	OUTPUT
cio_sck_o	Yes	Yes	T22,T201	Yes	T22,T201	OUTPUT
cio_sck_en_o	Yes	Yes	T51	Yes	T22,T51,T201	OUTPUT
cio_csb_o	Yes	Yes	T22,T201	Yes	T22,T201	OUTPUT
cio_csb_en_o	Yes	Yes	T51	Yes	T22,T51,T201	OUTPUT
cio_sd_o[0]	Yes	Yes	*T22,*T201	Yes	T22,T201	OUTPUT
cio_sd_o[3:1]	No	No		No		OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T22,*T201	Yes	T22,T201	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T22,T14,T15	Yes	T11,T22,T14	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_spi_event_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	31	70.45
Total Bits	352	298	84.66
Total Bits 0->1	176	149	84.66
Total Bits 1->0	176	149	84.66

Ports	44	31	70.45
Port Bits	352	298	84.66
Port Bits 0->1	176	149	84.66
Port Bits 1->0	176	149	84.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T53	Yes	T10,T11,T53	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T75,*T10,*T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T75,*T10,*T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T10,T11,T53	Yes	T10,T11,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T75,*T10,*T11	Yes	T75,T10,T11	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T51,*T75,*T10	Yes	T51,T75,T10	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T10,*T132,*T134	Yes	T10,T132,T134	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_i.a_valid	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	INPUT
tl_o.a_ready	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T75,*T10	Yes	T51,T75,T10	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T75,*T10,*T11	Yes	T75,T10,T11	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T75,T10,T11	Yes	T75,T10,T11	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T196,T36,T53	Yes	T196,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T196,T36,T133	Yes	T196,T36,T133	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T196,T36,T133	Yes	T196,T36,T133	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T196,T36,T53	Yes	T196,T36,T53	OUTPUT
cio_sck_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sck_en_o	Yes	Yes	T10,T12,T132	Yes	T10,T11,T12	OUTPUT
cio_csb_o	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_csb_en_o	Yes	Yes	T10,T12,T132	Yes	T10,T11,T12	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T10,*T11,*T12	Yes	T10,T11,T12	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T10,*T12,*T132	Yes	T10,T12,T132	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T10,T7,T12	Yes	T10,T7,T12	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T10,T12,T24	Yes	T10,T12,T24	INPUT
passthrough_i.passthrough_en	Yes	Yes	T10,T132,T134	Yes	T10,T12,T132	INPUT
passthrough_o.s[3:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
intr_error_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT
intr_spi_event_o	Yes	Yes	T135,T136,T137	Yes	T135,T136,T137	OUTPUT

*Tests covering at least one bit in the range