Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	44809151	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	44809151	0	0
T1	219553	25568	0	0
T2	211838	21085	0	0
T3	181656	19821	0	0
T4	161700	11662	0	0
T21	252348	32922	0	0
T50	152032	54328	0	0
T59	162507	23745	0	0
T62	281040	36924	0	0
T74	331003	39501	0	0
T75	648003	63798	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	34146569	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	34146569	0	0
T1	219553	22689	0	0
T2	211838	14581	0	0
T3	181656	15886	0	0
T4	161700	7795	0	0
T21	252348	23450	0	0
T50	152032	50330	0	0
T59	162507	17556	0	0
T62	281040	27347	0	0
T74	331003	35204	0	0
T75	648003	50109	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	33208020	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	33208020	0	0
T1	219553	13290	0	0
T2	211838	11129	0	0
T3	181656	7549	0	0
T4	161700	6328	0	0
T21	252348	16882	0	0
T50	152032	43852	0	0
T59	162507	9979	0	0
T62	281040	19685	0	0
T74	331003	30395	0	0
T75	648003	32077	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	27413307	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	27413307	0	0
T1	219553	13094	0	0
T2	211838	10750	0	0
T3	181656	7301	0	0
T4	161700	6074	0	0
T21	252348	16519	0	0
T50	152032	43679	0	0
T59	162507	9711	0	0
T62	281040	19300	0	0
T74	331003	30117	0	0
T75	648003	31309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	62244	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	62244	0	0
T1	219553	101	0	0
T2	211838	75	0	0
T3	181656	29	0	0
T4	161700	34	0	0
T21	252348	149	0	0
T50	152032	29	0	0
T59	162507	26	0	0
T62	281040	149	0	0
T74	331003	23	0	0
T75	648003	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	62243	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	62243	0	0
T1	219553	101	0	0
T2	211838	75	0	0
T3	181656	29	0	0
T4	161700	34	0	0
T21	252348	149	0	0
T50	152032	29	0	0
T59	162507	26	0	0
T62	281040	149	0	0
T74	331003	23	0	0
T75	648003	181	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	49824	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	49824	0	0
T1	219553	16	0	0
T2	211838	72	0	0
T3	181656	27	0	0
T4	161700	32	0	0
T21	252348	95	0	0
T50	152032	28	0	0
T59	162507	23	0	0
T62	281040	95	0	0
T74	331003	20	0	0
T75	648003	176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	49823	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	49823	0	0
T1	219553	16	0	0
T2	211838	72	0	0
T3	181656	27	0	0
T4	161700	32	0	0
T21	252348	95	0	0
T50	152032	28	0	0
T59	162507	23	0	0
T62	281040	95	0	0
T74	331003	20	0	0
T75	648003	176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	12420	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	12420	0	0
T1	219553	85	0	0
T2	211838	3	0	0
T3	181656	2	0	0
T4	161700	2	0	0
T21	252348	54	0	0
T50	152032	1	0	0
T59	162507	3	0	0
T62	281040	54	0	0
T74	331003	3	0	0
T75	648003	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375370805	12420	0	0
DepthKnown_A	375370805	375269793	0	0
RvalidKnown_A	375370805	375269793	0	0
WreadyKnown_A	375370805	375269793	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	12420	0	0
T1	219553	85	0	0
T2	211838	3	0	0
T3	181656	2	0	0
T4	161700	2	0	0
T21	252348	54	0	0
T50	152032	1	0	0
T59	162507	3	0	0
T62	281040	54	0	0
T74	331003	3	0	0
T75	648003	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	375269793	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0