Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.13 94.13

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main 94.16 94.16
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 94.71 94.71


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.16 94.16


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.16 94.16


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.05 90.65 91.52 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.71 94.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.71 94.71


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.05 90.65 91.52 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 45 70.31
Total Bits 1158 1090 94.13
Total Bits 0->1 579 545 94.13
Total Bits 1->0 579 545 94.13

Ports 64 45 70.31
Port Bits 1158 1090 94.13
Port Bits 0->1 579 545 94.13
Port Bits 1->0 579 545 94.13

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T21 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T28,*T6,*T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
regs_tl_o.a_ready Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes T60,T190,T105 Yes T60,T190,T105 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T60,T25,T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T60,*T25,*T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T60,T25,T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T51,*T60,*T26 Yes T51,T60,T28 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T60,T25,T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T60,*T190,*T105 Yes T60,T170,T82 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T36,T53,T37 Yes T36,T53,T37 INPUT
alert_rx_i[0].ping_n Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
alert_rx_i[0].ping_p Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T36,T53,T37 Yes T36,T53,T37 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T21,T62,T63 Yes T21,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T21 INPUT
sram_otp_key_o.req Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T21 Yes T2,T21,T50 INPUT
sram_otp_key_i.ack Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 40 66.67
Total Bits 1130 1064 94.16
Total Bits 0->1 565 532 94.16
Total Bits 1->0 565 532 94.16

Ports 60 40 66.67
Port Bits 1130 1064 94.16
Port Bits 0->1 565 532 94.16
Port Bits 1->0 565 532 94.16

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[5] No No No INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[0] No No No INPUT
ram_tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T21 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T28,T6,T25 Yes T28,T6,T25 INPUT
regs_tl_i.a_user.cmd_intg[0] Yes Yes *T28,*T6,*T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_user.cmd_intg[1] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:2] Yes Yes T170,T82,T171 Yes T170,T82,T171 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T28,*T6,*T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T28,T6,T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T28,T6,T25 Yes T28,T6,T25 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T28,T6,T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes *T28,*T6,*T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T28,T6,T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T28,*T6,*T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T28,*T6,*T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[1:0] Yes Yes *T51,*T170,*T82 Yes T51,T170,T82 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T28,T6,T170 Yes T28,T6,T170 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T170,T82,T171 Yes T170,T82,T171 INPUT
regs_tl_i.a_valid Yes Yes T28,T6,T170 Yes T28,T6,T170 INPUT
regs_tl_o.a_ready Yes Yes T28,T6,T170 Yes T28,T6,T170 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T172,*T51,*T173 Yes T172,T51,T173 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T25,T26,T27 Yes T28,T6,T25 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T25,*T26,*T27 Yes T28,T6,T170 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T25,T26,T27 Yes T28,T6,T25 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T51,*T105,*T174 Yes T51,T170,T82 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T25,T26,T27 Yes T28,T6,T170 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T105,*T174,*T172 Yes T170,T82,T171 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T28,T6,T170 Yes T28,T6,T170 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T36,T53,T37 Yes T36,T53,T37 INPUT
alert_rx_i[0].ping_n Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
alert_rx_i[0].ping_p Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T36,T53,T37 Yes T36,T53,T37 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T21,T62,T63 Yes T21,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T21 INPUT
sram_otp_key_o.req Yes Yes T28,T6,T25 Yes T28,T6,T25 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T21 Yes T2,T21,T50 INPUT
sram_otp_key_i.ack Yes Yes T28,T6,T25 Yes T28,T6,T25 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 42 72.41
Total Bits 1096 1038 94.71
Total Bits 0->1 548 519 94.71
Total Bits 1->0 548 519 94.71

Ports 58 42 72.41
Port Bits 1096 1038 94.71
Port Bits 0->1 548 519 94.71
Port Bits 1->0 548 519 94.71

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[11:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T21 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[1:0] Yes Yes *T35,*T167,*T141 Yes T35,T167,T141 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[19:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
regs_tl_o.a_ready Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes T60,T190,*T105 Yes T60,T190,T105 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T60,T25,T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T60,*T25,*T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T60,T25,T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T51,*T60,*T26 Yes T51,T60,T28 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T60,T25,T26 Yes T60,T28,T6 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T60,*T190,*T105 Yes T60,T170,T82 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T36,T53,T37 Yes T36,T53,T37 INPUT
alert_rx_i[0].ping_n Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
alert_rx_i[0].ping_p Yes Yes T36,T37,T38 Yes T36,T37,T38 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T36,T53,T37 Yes T36,T53,T37 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T21,T62,T63 Yes T21,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T60,T190,T105 Yes T60,T190,T105 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T21 Yes T2,T21,T50 INPUT
sram_otp_key_i.ack Yes Yes T60,T190,T105 Yes T60,T190,T105 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%