Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.07			90.07
tb.dut.top_earlgrey.u_uart1	90.13			90.13
tb.dut.top_earlgrey.u_uart2	90.13			90.13
tb.dut.top_earlgrey.u_uart3	90.20			90.20

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.05	90.65		91.52			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	INPUT
tl_o.a_ready	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T75,T295,T212	Yes	T75,T295,T212	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T295,T212	Yes	T75,T295,T28	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T75,T25,T26	Yes	T75,T295,T28	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T75,T295,T212	Yes	T75,T295,T28	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T75,*T295	Yes	T51,T75,T295	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T75,T25,T26	Yes	T75,T295,T28	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T75,*T295,*T212	Yes	T75,T295,T212	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T294,T36,T53	Yes	T294,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T37,T330	Yes	T36,T37,T38	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T37,T38	Yes	T36,T37,T330	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T294,T36,T53	Yes	T294,T36,T53	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T295,T212,T128	Yes	T295,T212,T128	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T295,T212,T128	Yes	T295,T212,T128	OUTPUT
intr_rx_watermark_o	Yes	Yes	T295,T212,T128	Yes	T295,T212,T128	OUTPUT
intr_tx_empty_o	Yes	Yes	T295,T212,T128	Yes	T295,T212,T128	OUTPUT
intr_rx_overflow_o	Yes	Yes	T295,T212,T128	Yes	T295,T212,T128	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_break_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_timeout_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	INPUT
tl_o.a_ready	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T75,T295,T25	Yes	T75,T295,T25	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T295,T25	Yes	T75,T295,T28	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T75,T25,T26	Yes	T75,T295,T28	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T75,T295,T25	Yes	T75,T295,T28	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T75,*T295	Yes	T51,T75,T295	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T75,T25,T26	Yes	T75,T295,T28	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T75,*T295,*T25	Yes	T75,T295,T25	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T75,T295,T28	Yes	T75,T295,T28	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T36,T53,T331	Yes	T36,T53,T331	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T36,T53,T331	Yes	T36,T53,T331	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T295,T25,T332	Yes	T295,T25,T332	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T295,T332,T333	Yes	T295,T332,T333	OUTPUT
intr_rx_watermark_o	Yes	Yes	T295,T332,T333	Yes	T295,T332,T333	OUTPUT
intr_tx_empty_o	Yes	Yes	T295,T332,T333	Yes	T295,T332,T333	OUTPUT
intr_rx_overflow_o	Yes	Yes	T295,T332,T333	Yes	T295,T332,T333	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_break_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_timeout_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T212,T53,T92	Yes	T212,T53,T92	INPUT
tl_o.a_ready	Yes	Yes	T212,T53,T92	Yes	T212,T53,T92	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T212,T92,T213	Yes	T212,T53,T92	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T220,*T51	Yes	T212,T53,T92	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T212,T92,T213	Yes	T212,T53,T92	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T212,*T92	Yes	T51,T212,T92	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T220,T51	Yes	T212,T53,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T212,*T213,*T214	Yes	T212,T213,T214	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T212,T53,T92	Yes	T212,T53,T92	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T294,T36,T53	Yes	T294,T36,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T294,T36,T53	Yes	T294,T36,T53	OUTPUT
cio_rx_i	Yes	Yes	T212,T22,T213	Yes	T212,T11,T22	INPUT
cio_tx_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_tx_empty_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_rx_overflow_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_break_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_timeout_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T128,T129,T53	Yes	T128,T129,T53	INPUT
tl_o.a_ready	Yes	Yes	T128,T129,T53	Yes	T128,T129,T53	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T128,T129,T92	Yes	T128,T129,T53	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T220,*T51	Yes	T128,T129,T53	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T128,T129,T92	Yes	T128,T129,T53	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T128,*T129	Yes	T51,T128,T129	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T220,T51	Yes	T128,T129,T53	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T128,*T129,*T314	Yes	T128,T129,T314	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T128,T129,T53	Yes	T128,T129,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T36,T53,T92	Yes	T36,T53,T92	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T36,T53,T92	Yes	T36,T53,T92	OUTPUT
cio_rx_i	Yes	Yes	T128,T129,T14	Yes	T128,T129,T14	INPUT
cio_tx_o	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	OUTPUT
intr_rx_watermark_o	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	OUTPUT
intr_tx_empty_o	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	OUTPUT
intr_rx_overflow_o	Yes	Yes	T128,T129,T314	Yes	T128,T129,T314	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_break_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_timeout_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T315,T198	Yes	T13,T315,T198	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T315,T198	Yes	T13,T315,T198	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T29,*T6,*T30	Yes	T29,T6,T30	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T20	Yes	T14,T15,T20	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T15,*T20	Yes	T14,T15,T20	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T53,T13,T92	Yes	T53,T13,T92	INPUT
tl_o.a_ready	Yes	Yes	T53,T13,T92	Yes	T53,T13,T92	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T315,T198	Yes	T13,T315,T198	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T13,T92,T315	Yes	T53,T13,T92	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T92,*T220,T51	Yes	T53,T13,T92	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T92,T315	Yes	T53,T13,T92	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T51,*T13,*T92	Yes	T51,T13,T92	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T92,T220,T51	Yes	T53,T13,T92	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T315,*T198	Yes	T13,T315,T198	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T53,T13,T92	Yes	T53,T13,T92	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T36,T53,T334	Yes	T36,T53,T334	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T36,T37,T330	Yes	T36,T37,T38	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T36,T37,T38	Yes	T36,T37,T330	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T36,T53,T334	Yes	T36,T53,T334	OUTPUT
cio_rx_i	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
cio_tx_o	Yes	Yes	T13,T315,T335	Yes	T13,T315,T335	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T315,T198	Yes	T13,T315,T198	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T315,T198	Yes	T13,T315,T198	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T315,T198	Yes	T13,T315,T198	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T315,T198	Yes	T13,T315,T198	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_break_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_timeout_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT

*Tests covering at least one bit in the range