Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_otp_ctrl.u_reg_core.u_err_code_3

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_alert_test

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_invert_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_virtual_od_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_select_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_keeper_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_schmitt_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_od_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_slew_rate_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_drive_strength_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_invert_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_virtual_od_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_select_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_keeper_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_schmitt_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_od_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_slew_rate_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	40.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_drive_strength_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_invert_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_virtual_od_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_select_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_keeper_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_schmitt_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_od_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_slew_rate_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_drive_strength_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_invert_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_virtual_od_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.51	98.18	67.84			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_alert_test

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26		unreachable
27		unreachable
28	1	1
29	1	1
30		unreachable

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_invert_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_virtual_od_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_pull_select_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_keeper_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_schmitt_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_od_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_slew_rate_0

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_0_drive_strength_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_invert_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_virtual_od_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_pull_select_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_keeper_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_schmitt_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_od_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_slew_rate_1

	Line No.	Total	Covered	Percent
TOTAL		5	2	40.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_1_drive_strength_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_invert_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_virtual_od_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_pull_select_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_keeper_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_schmitt_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_od_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_slew_rate_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	0	1
27	0	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_2_drive_strength_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	1	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_invert_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_3_virtual_od_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_ext.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
29	1	1
30	0	1