Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_peri
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.73 89.73

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_peri 89.73 89.73



Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.73 89.73


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.73 89.73


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.05 90.65 91.52 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_peri
TotalCoveredPercent
Totals 562 368 65.48
Total Bits 7060 6335 89.73
Total Bits 0->1 3530 3168 89.75
Total Bits 1->0 3530 3167 89.72

Ports 562 368 65.48
Port Bits 7060 6335 89.73
Port Bits 0->1 3530 3168 89.75
Port Bits 1->0 3530 3167 89.72

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_peri_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_peri_ni Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_main_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.instr_type[2:1] No No No INPUT
tl_main_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_main_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_main_i.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 INPUT
tl_main_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_main_i.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 INPUT
tl_main_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_main_i.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 INPUT
tl_main_i.a_opcode[1] No No No INPUT
tl_main_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_error Yes Yes T21,T62,T63 Yes T21,T62,T63 OUTPUT
tl_main_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_user.rsp_intg[6] No No No OUTPUT
tl_main_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_sink No No No OUTPUT
tl_main_o.d_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_main_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_main_o.d_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_main_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_main_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_main_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.data_intg[6:0] Yes Yes T75,T295,T28 Yes T75,T295,T28 OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_uart0_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_data[31:0] Yes Yes T75,T295,T28 Yes T75,T295,T28 OUTPUT
tl_uart0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_uart0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_uart0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_uart0_o.a_opcode[1] No No No OUTPUT
tl_uart0_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_valid Yes Yes T75,T295,T28 Yes T75,T295,T28 OUTPUT
tl_uart0_i.a_ready Yes Yes T75,T295,T28 Yes T75,T295,T28 INPUT
tl_uart0_i.d_error No No No INPUT
tl_uart0_i.d_user.data_intg[6:0] Yes Yes T75,T295,T25 Yes T75,T295,T25 INPUT
tl_uart0_i.d_user.rsp_intg[1:0] Yes Yes T75,T295,T25 Yes T75,T295,T28 INPUT
tl_uart0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_uart0_i.d_user.rsp_intg[5:4] Yes Yes T75,T25,T26 Yes T75,T295,T28 INPUT
tl_uart0_i.d_user.rsp_intg[6] No No No INPUT
tl_uart0_i.d_data[31:0] Yes Yes T75,T295,T25 Yes T75,T295,T28 INPUT
tl_uart0_i.d_sink No No No INPUT
tl_uart0_i.d_source[1:0] Yes Yes *T51,*T75,*T295 Yes T51,T75,T295 INPUT
tl_uart0_i.d_source[5:2] No No No INPUT
tl_uart0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_uart0_i.d_size[0] No No No INPUT
tl_uart0_i.d_size[1] Yes Yes T75,T25,T26 Yes T75,T295,T28 INPUT
tl_uart0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart0_i.d_opcode[0] Yes Yes *T75,*T295,*T25 Yes T75,T295,T25 INPUT
tl_uart0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart0_i.d_valid Yes Yes T75,T295,T28 Yes T75,T295,T28 INPUT
tl_uart1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.data_intg[6:0] Yes Yes T212,T213,T214 Yes T212,T213,T214 OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_uart1_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_data[31:0] Yes Yes T212,T213,T214 Yes T212,T213,T214 OUTPUT
tl_uart1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_uart1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_uart1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_uart1_o.a_opcode[1] No No No OUTPUT
tl_uart1_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_valid Yes Yes T212,T53,T92 Yes T212,T53,T92 OUTPUT
tl_uart1_i.a_ready Yes Yes T212,T53,T92 Yes T212,T53,T92 INPUT
tl_uart1_i.d_error No No No INPUT
tl_uart1_i.d_user.data_intg[6:0] Yes Yes T212,T213,T214 Yes T212,T213,T214 INPUT
tl_uart1_i.d_user.rsp_intg[1:0] Yes Yes T212,T92,T213 Yes T212,T53,T92 INPUT
tl_uart1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_uart1_i.d_user.rsp_intg[5:4] Yes Yes *T92,*T220,*T51 Yes T212,T53,T92 INPUT
tl_uart1_i.d_user.rsp_intg[6] No No No INPUT
tl_uart1_i.d_data[31:0] Yes Yes T212,T92,T213 Yes T212,T53,T92 INPUT
tl_uart1_i.d_sink No No No INPUT
tl_uart1_i.d_source[1:0] Yes Yes *T51,*T212,*T92 Yes T51,T212,T92 INPUT
tl_uart1_i.d_source[5:2] No No No INPUT
tl_uart1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_uart1_i.d_size[0] No No No INPUT
tl_uart1_i.d_size[1] Yes Yes T92,T220,T51 Yes T212,T53,T92 INPUT
tl_uart1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart1_i.d_opcode[0] Yes Yes *T212,*T213,*T214 Yes T212,T213,T214 INPUT
tl_uart1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart1_i.d_valid Yes Yes T212,T53,T92 Yes T212,T53,T92 INPUT
tl_uart2_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.data_intg[6:0] Yes Yes T128,T129,T314 Yes T128,T129,T314 OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.instr_type[2:1] No No No OUTPUT
tl_uart2_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_data[31:0] Yes Yes T128,T129,T314 Yes T128,T129,T314 OUTPUT
tl_uart2_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_uart2_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_uart2_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_uart2_o.a_opcode[1] No No No OUTPUT
tl_uart2_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_valid Yes Yes T128,T129,T53 Yes T128,T129,T53 OUTPUT
tl_uart2_i.a_ready Yes Yes T128,T129,T53 Yes T128,T129,T53 INPUT
tl_uart2_i.d_error No No No INPUT
tl_uart2_i.d_user.data_intg[6:0] Yes Yes T128,T129,T314 Yes T128,T129,T314 INPUT
tl_uart2_i.d_user.rsp_intg[1:0] Yes Yes T128,T129,T92 Yes T128,T129,T53 INPUT
tl_uart2_i.d_user.rsp_intg[3:2] No No No INPUT
tl_uart2_i.d_user.rsp_intg[5:4] Yes Yes *T92,*T220,*T51 Yes T128,T129,T53 INPUT
tl_uart2_i.d_user.rsp_intg[6] No No No INPUT
tl_uart2_i.d_data[31:0] Yes Yes T128,T129,T92 Yes T128,T129,T53 INPUT
tl_uart2_i.d_sink No No No INPUT
tl_uart2_i.d_source[1:0] Yes Yes *T51,*T128,*T129 Yes T51,T128,T129 INPUT
tl_uart2_i.d_source[5:2] No No No INPUT
tl_uart2_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_uart2_i.d_size[0] No No No INPUT
tl_uart2_i.d_size[1] Yes Yes T92,T220,T51 Yes T128,T129,T53 INPUT
tl_uart2_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart2_i.d_opcode[0] Yes Yes *T128,*T129,*T314 Yes T128,T129,T314 INPUT
tl_uart2_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart2_i.d_valid Yes Yes T128,T129,T53 Yes T128,T129,T53 INPUT
tl_uart3_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.data_intg[6:0] Yes Yes T13,T315,T198 Yes T13,T315,T198 OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.instr_type[2:1] No No No OUTPUT
tl_uart3_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_data[31:0] Yes Yes T13,T315,T198 Yes T13,T315,T198 OUTPUT
tl_uart3_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_uart3_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_uart3_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_uart3_o.a_opcode[1] No No No OUTPUT
tl_uart3_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_valid Yes Yes T53,T13,T92 Yes T53,T13,T92 OUTPUT
tl_uart3_i.a_ready Yes Yes T53,T13,T92 Yes T53,T13,T92 INPUT
tl_uart3_i.d_error No No No INPUT
tl_uart3_i.d_user.data_intg[6:0] Yes Yes T13,T315,T198 Yes T13,T315,T198 INPUT
tl_uart3_i.d_user.rsp_intg[1:0] Yes Yes T13,T92,T315 Yes T53,T13,T92 INPUT
tl_uart3_i.d_user.rsp_intg[3:2] No No No INPUT
tl_uart3_i.d_user.rsp_intg[5:4] Yes Yes *T92,*T220,T51 Yes T53,T13,T92 INPUT
tl_uart3_i.d_user.rsp_intg[6] No No No INPUT
tl_uart3_i.d_data[31:0] Yes Yes T13,T92,T315 Yes T53,T13,T92 INPUT
tl_uart3_i.d_sink No No No INPUT
tl_uart3_i.d_source[1:0] Yes Yes *T51,*T13,*T92 Yes T51,T13,T92 INPUT
tl_uart3_i.d_source[5:2] No No No INPUT
tl_uart3_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_uart3_i.d_size[0] No No No INPUT
tl_uart3_i.d_size[1] Yes Yes T92,T220,T51 Yes T53,T13,T92 INPUT
tl_uart3_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart3_i.d_opcode[0] Yes Yes *T13,*T315,*T198 Yes T13,T315,T198 INPUT
tl_uart3_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart3_i.d_valid Yes Yes T53,T13,T92 Yes T53,T13,T92 INPUT
tl_i2c0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.data_intg[6:0] Yes Yes T211,T131,T316 Yes T211,T131,T316 OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_i2c0_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_data[31:0] Yes Yes T211,T131,T316 Yes T211,T131,T316 OUTPUT
tl_i2c0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_i2c0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_i2c0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_i2c0_o.a_opcode[1] No No No OUTPUT
tl_i2c0_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_valid Yes Yes T211,T53,T92 Yes T211,T53,T92 OUTPUT
tl_i2c0_i.a_ready Yes Yes T211,T53,T92 Yes T211,T53,T92 INPUT
tl_i2c0_i.d_error No No No INPUT
tl_i2c0_i.d_user.data_intg[6:0] Yes Yes T211,T316,T204 Yes T211,T316,T204 INPUT
tl_i2c0_i.d_user.rsp_intg[1:0] Yes Yes T211,T92,T220 Yes T211,T53,T92 INPUT
tl_i2c0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_i2c0_i.d_user.rsp_intg[5:4] Yes Yes *T92,*T220,T131 Yes T211,T53,T92 INPUT
tl_i2c0_i.d_user.rsp_intg[6] No No No INPUT
tl_i2c0_i.d_data[31:0] Yes Yes T211,T92,T220 Yes T211,T53,T92 INPUT
tl_i2c0_i.d_sink No No No INPUT
tl_i2c0_i.d_source[1:0] Yes Yes *T149,*T52,*T211 Yes T149,T52,T211 INPUT
tl_i2c0_i.d_source[5:2] No No No INPUT
tl_i2c0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i2c0_i.d_size[0] No No No INPUT
tl_i2c0_i.d_size[1] Yes Yes T92,T220,T131 Yes T211,T53,T92 INPUT
tl_i2c0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c0_i.d_opcode[0] Yes Yes *T211,*T131,*T316 Yes T211,T131,T316 INPUT
tl_i2c0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c0_i.d_valid Yes Yes T211,T53,T92 Yes T211,T53,T92 INPUT
tl_i2c1_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.data_intg[6:0] Yes Yes T131,T317,T318 Yes T131,T317,T318 OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_i2c1_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_data[31:0] Yes Yes T131,T317,T318 Yes T131,T317,T318 OUTPUT
tl_i2c1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_i2c1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_i2c1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_i2c1_o.a_opcode[1] No No No OUTPUT
tl_i2c1_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_valid Yes Yes T53,T92,T220 Yes T53,T92,T220 OUTPUT
tl_i2c1_i.a_ready Yes Yes T53,T92,T220 Yes T53,T92,T220 INPUT
tl_i2c1_i.d_error No No No INPUT
tl_i2c1_i.d_user.data_intg[6:0] Yes Yes T131,T317,T318 Yes T131,T317,T318 INPUT
tl_i2c1_i.d_user.rsp_intg[1:0] Yes Yes T92,T220,T131 Yes T53,T92,T220 INPUT
tl_i2c1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_i2c1_i.d_user.rsp_intg[5:4] Yes Yes *T92,*T220,T131 Yes T53,T92,T220 INPUT
tl_i2c1_i.d_user.rsp_intg[6] No No No INPUT
tl_i2c1_i.d_data[31:0] Yes Yes T92,T220,T131 Yes T53,T92,T220 INPUT
tl_i2c1_i.d_sink No No No INPUT
tl_i2c1_i.d_source[1:0] Yes Yes *T149,*T52,*T92 Yes T149,T52,T92 INPUT
tl_i2c1_i.d_source[5:2] No No No INPUT
tl_i2c1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i2c1_i.d_size[0] No No No INPUT
tl_i2c1_i.d_size[1] Yes Yes T92,T220,T131 Yes T53,T92,T220 INPUT
tl_i2c1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c1_i.d_opcode[0] Yes Yes *T131,*T317,*T318 Yes T131,T317,T318 INPUT
tl_i2c1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c1_i.d_valid Yes Yes T53,T92,T220 Yes T53,T92,T220 INPUT
tl_i2c2_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.data_intg[6:0] Yes Yes T74,T131,T319 Yes T74,T131,T319 OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.instr_type[2:1] No No No OUTPUT
tl_i2c2_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_data[31:0] Yes Yes T74,T131,T319 Yes T74,T131,T319 OUTPUT
tl_i2c2_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_i2c2_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_i2c2_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_i2c2_o.a_opcode[1] No No No OUTPUT
tl_i2c2_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_valid Yes Yes T74,T53,T92 Yes T74,T53,T92 OUTPUT
tl_i2c2_i.a_ready Yes Yes T74,T53,T92 Yes T74,T53,T92 INPUT
tl_i2c2_i.d_error No No No INPUT
tl_i2c2_i.d_user.data_intg[6:0] Yes Yes T74,T319,T204 Yes T74,T319,T204 INPUT
tl_i2c2_i.d_user.rsp_intg[1:0] Yes Yes T74,T92,T220 Yes T74,T53,T92 INPUT
tl_i2c2_i.d_user.rsp_intg[3:2] No No No INPUT
tl_i2c2_i.d_user.rsp_intg[5:4] Yes Yes *T92,*T220,T131 Yes T74,T53,T92 INPUT
tl_i2c2_i.d_user.rsp_intg[6] No No No INPUT
tl_i2c2_i.d_data[31:0] Yes Yes T74,T92,T220 Yes T74,T53,T92 INPUT
tl_i2c2_i.d_sink No No No INPUT
tl_i2c2_i.d_source[1:0] Yes Yes *T149,*T52,*T74 Yes T149,T52,T74 INPUT
tl_i2c2_i.d_source[5:2] No No No INPUT
tl_i2c2_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i2c2_i.d_size[0] No No No INPUT
tl_i2c2_i.d_size[1] Yes Yes T92,T220,T131 Yes T74,T53,T92 INPUT
tl_i2c2_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c2_i.d_opcode[0] Yes Yes *T74,*T131,*T319 Yes T74,T131,T319 INPUT
tl_i2c2_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c2_i.d_valid Yes Yes T74,T53,T92 Yes T74,T53,T92 INPUT
tl_pattgen_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.data_intg[6:0] Yes Yes T216,T135,T320 Yes T216,T135,T320 OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.instr_type[2:1] No No No OUTPUT
tl_pattgen_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_data[31:0] Yes Yes T216,T135,T320 Yes T216,T135,T320 OUTPUT
tl_pattgen_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_pattgen_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_pattgen_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_pattgen_o.a_opcode[1] No No No OUTPUT
tl_pattgen_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_valid Yes Yes T216,T53,T135 Yes T216,T53,T135 OUTPUT
tl_pattgen_i.a_ready Yes Yes T216,T53,T135 Yes T216,T53,T135 INPUT
tl_pattgen_i.d_error No No No INPUT
tl_pattgen_i.d_user.data_intg[6:0] Yes Yes T216,T135,T320 Yes T216,T135,T320 INPUT
tl_pattgen_i.d_user.rsp_intg[1:0] Yes Yes T216,T135,T320 Yes T216,T53,T135 INPUT
tl_pattgen_i.d_user.rsp_intg[3:2] No No No INPUT
tl_pattgen_i.d_user.rsp_intg[5:4] Yes Yes T51,T52,*T216 Yes T216,T53,T135 INPUT
tl_pattgen_i.d_user.rsp_intg[6] No No No INPUT
tl_pattgen_i.d_data[31:0] Yes Yes T216,T135,T320 Yes T216,T53,T135 INPUT
tl_pattgen_i.d_sink No No No INPUT
tl_pattgen_i.d_source[1:0] Yes Yes *T51,*T52,*T216 Yes T51,T52,T216 INPUT
tl_pattgen_i.d_source[5:2] No No No INPUT
tl_pattgen_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_pattgen_i.d_size[0] No No No INPUT
tl_pattgen_i.d_size[1] Yes Yes T51,T52 Yes T216,T53,T135 INPUT
tl_pattgen_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pattgen_i.d_opcode[0] Yes Yes *T216,*T135,*T320 Yes T216,T135,T320 INPUT
tl_pattgen_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pattgen_i.d_valid Yes Yes T216,T53,T135 Yes T216,T53,T135 INPUT
tl_pwm_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0] Yes Yes T110,T296,T291 Yes T110,T296,T291 OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_pwm_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_data[31:0] Yes Yes T110,T296,T291 Yes T110,T296,T291 OUTPUT
tl_pwm_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_pwm_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_pwm_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_pwm_aon_o.a_opcode[1] No No No OUTPUT
tl_pwm_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_valid Yes Yes T53,T110,T296 Yes T53,T110,T296 OUTPUT
tl_pwm_aon_i.a_ready Yes Yes T53,T110,T296 Yes T53,T110,T296 INPUT
tl_pwm_aon_i.d_error No No No INPUT
tl_pwm_aon_i.d_user.data_intg[6:0] Yes Yes T110,T296,T291 Yes T110,T296,T291 INPUT
tl_pwm_aon_i.d_user.rsp_intg[1:0] Yes Yes T110,T296,T291 Yes T53,T110,T296 INPUT
tl_pwm_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_pwm_aon_i.d_user.rsp_intg[4] No No Yes T53,T110,T296 INPUT
tl_pwm_aon_i.d_user.rsp_intg[5] Yes Yes *T110,*T296,*T291 Yes T110,T296,T291 INPUT
tl_pwm_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_pwm_aon_i.d_data[31:0] Yes Yes T110,T296,T291 Yes T53,T110,T296 INPUT
tl_pwm_aon_i.d_sink No No No INPUT
tl_pwm_aon_i.d_source[0] No No No INPUT
tl_pwm_aon_i.d_source[1] Yes Yes *T110,*T296,*T291 Yes T110,T296,T291 INPUT
tl_pwm_aon_i.d_source[5:2] No No No INPUT
tl_pwm_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_pwm_aon_i.d_size[0] No No No INPUT
tl_pwm_aon_i.d_size[1] No No Yes T53,T110,T296 INPUT
tl_pwm_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pwm_aon_i.d_opcode[0] Yes Yes *T110,*T296,*T291 Yes T110,T296,T291 INPUT
tl_pwm_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pwm_aon_i.d_valid Yes Yes T53,T110,T296 Yes T53,T110,T296 INPUT
tl_gpio_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.data_intg[6:0] Yes Yes T28,T25,T26 Yes T28,T25,T26 OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.instr_type[2:1] No No No OUTPUT
tl_gpio_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_gpio_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_gpio_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_gpio_o.a_opcode[1] No No No OUTPUT
tl_gpio_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_error No No No INPUT
tl_gpio_i.d_user.data_intg[6:0] Yes Yes T321,T322,T204 Yes T321,T322,T204 INPUT
tl_gpio_i.d_user.rsp_intg[1:0] Yes Yes T110,T321,T322 Yes T53,T110,T291 INPUT
tl_gpio_i.d_user.rsp_intg[3:2] No No No INPUT
tl_gpio_i.d_user.rsp_intg[5:4] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_gpio_i.d_user.rsp_intg[6] No No No INPUT
tl_gpio_i.d_data[31:0] Yes Yes T110,T321,T322 Yes T53,T110,T291 INPUT
tl_gpio_i.d_sink No No No INPUT
tl_gpio_i.d_source[1:0] Yes Yes *T149,*T52,*T25 Yes T149,T52,T28 INPUT
tl_gpio_i.d_source[5:2] No No No INPUT
tl_gpio_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_gpio_i.d_size[0] No No No INPUT
tl_gpio_i.d_size[1] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_gpio_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_gpio_i.d_opcode[0] Yes Yes *T2,*T3,*T21 Yes T1,T2,T3 INPUT
tl_gpio_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_gpio_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.data_intg[6:0] Yes Yes T10,T12,T24 Yes T10,T12,T24 OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_device_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_data[31:0] Yes Yes T10,T12,T24 Yes T10,T12,T24 OUTPUT
tl_spi_device_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_spi_device_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_spi_device_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_spi_device_o.a_opcode[1] No No No OUTPUT
tl_spi_device_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_valid Yes Yes T10,T53,T12 Yes T10,T53,T12 OUTPUT
tl_spi_device_i.a_ready Yes Yes T10,T53,T12 Yes T10,T53,T12 INPUT
tl_spi_device_i.d_error No No No INPUT
tl_spi_device_i.d_user.data_intg[6:0] Yes Yes T10,T12,T24 Yes T10,T12,T24 INPUT
tl_spi_device_i.d_user.rsp_intg[1:0] Yes Yes T10,T12,T24 Yes T10,T12,T24 INPUT
tl_spi_device_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_device_i.d_user.rsp_intg[5:4] Yes Yes T10,T131,T132 Yes T10,T53,T12 INPUT
tl_spi_device_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_device_i.d_data[31:0] Yes Yes T10,T53,T12 Yes T10,T12,T24 INPUT
tl_spi_device_i.d_sink No No No INPUT
tl_spi_device_i.d_source[1:0] Yes Yes *T51,*T10,*T12 Yes T51,T10,T53 INPUT
tl_spi_device_i.d_source[5:2] No No No INPUT
tl_spi_device_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_device_i.d_size[0] No No No INPUT
tl_spi_device_i.d_size[1] Yes Yes T10,T131,T132 Yes T10,T53,T12 INPUT
tl_spi_device_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_device_i.d_opcode[0] Yes Yes *T10,*T53,*T12 Yes T10,T12,T24 INPUT
tl_spi_device_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_device_i.d_valid Yes Yes T10,T53,T12 Yes T10,T53,T12 INPUT
tl_rv_timer_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0] Yes Yes T233,T110,T231 Yes T233,T110,T231 OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_timer_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_data[31:0] Yes Yes T233,T110,T231 Yes T233,T110,T231 OUTPUT
tl_rv_timer_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_rv_timer_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_rv_timer_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_rv_timer_o.a_opcode[1] No No No OUTPUT
tl_rv_timer_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_valid Yes Yes T233,T53,T110 Yes T233,T53,T110 OUTPUT
tl_rv_timer_i.a_ready Yes Yes T233,T53,T110 Yes T233,T53,T110 INPUT
tl_rv_timer_i.d_error No No No INPUT
tl_rv_timer_i.d_user.data_intg[6:0] Yes Yes T233,T231,T135 Yes T233,T231,T135 INPUT
tl_rv_timer_i.d_user.rsp_intg[1:0] Yes Yes T233,T110,T231 Yes T233,T53,T110 INPUT
tl_rv_timer_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_timer_i.d_user.rsp_intg[5:4] Yes Yes T110,*T313,*T51 Yes T233,T53,T110 INPUT
tl_rv_timer_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_timer_i.d_data[31:0] Yes Yes T233,T110,T231 Yes T233,T53,T110 INPUT
tl_rv_timer_i.d_sink No No No INPUT
tl_rv_timer_i.d_source[1:0] Yes Yes *T51,*T233,*T110 Yes T51,T233,T110 INPUT
tl_rv_timer_i.d_source[5:2] No No No INPUT
tl_rv_timer_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_timer_i.d_size[0] No No No INPUT
tl_rv_timer_i.d_size[1] Yes Yes T110,T313,T51 Yes T233,T53,T110 INPUT
tl_rv_timer_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_timer_i.d_opcode[0] Yes Yes *T233,*T110,*T231 Yes T233,T110,T231 INPUT
tl_rv_timer_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_timer_i.d_valid Yes Yes T233,T53,T110 Yes T233,T53,T110 INPUT
tl_pwrmgr_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0] Yes Yes T2,T3,T59 Yes T2,T3,T59 OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_data[31:0] Yes Yes T2,T3,T59 Yes T2,T3,T59 OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_pwrmgr_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_pwrmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_pwrmgr_aon_o.a_opcode[1] No No No OUTPUT
tl_pwrmgr_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_valid Yes Yes T2,T3,T59 Yes T2,T3,T59 OUTPUT
tl_pwrmgr_aon_i.a_ready Yes Yes T2,T3,T59 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_error No No No INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0] Yes Yes T2,T3,T59 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[1:0] Yes Yes T2,T3,T59 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[5:4] Yes Yes *T25,*T26,*T27 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_pwrmgr_aon_i.d_data[31:0] Yes Yes T2,T3,T59 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_sink No No No INPUT
tl_pwrmgr_aon_i.d_source[0] No No No INPUT
tl_pwrmgr_aon_i.d_source[1] Yes Yes *T2,*T3,*T59 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_source[5:2] No No No INPUT
tl_pwrmgr_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_pwrmgr_aon_i.d_size[0] No No No INPUT
tl_pwrmgr_aon_i.d_size[1] Yes Yes T25,T26,T27 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pwrmgr_aon_i.d_opcode[0] Yes Yes *T2,*T3,*T59 Yes T2,T3,T59 INPUT
tl_pwrmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pwrmgr_aon_i.d_valid Yes Yes T2,T3,T59 Yes T2,T3,T59 INPUT
tl_rstmgr_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_rstmgr_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_rstmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_rstmgr_aon_o.a_opcode[1] No No No OUTPUT
tl_rstmgr_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_error No No No INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[1:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[5:4] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_rstmgr_aon_i.d_data[31:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_sink No No No INPUT
tl_rstmgr_aon_i.d_source[0] No No No INPUT
tl_rstmgr_aon_i.d_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_source[5:2] No No No INPUT
tl_rstmgr_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rstmgr_aon_i.d_size[0] No No No INPUT
tl_rstmgr_aon_i.d_size[1] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rstmgr_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rstmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0] Yes Yes T75,T295,T67 Yes T75,T295,T67 OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_data[31:0] Yes Yes T75,T295,T67 Yes T75,T295,T67 OUTPUT
tl_clkmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_clkmgr_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_clkmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_clkmgr_aon_o.a_opcode[1] No No No OUTPUT
tl_clkmgr_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_error No No No INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0] Yes Yes T295,T67,T212 Yes T295,T67,T212 INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[1:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[5:4] Yes Yes *T2,*T3,*T21 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_clkmgr_aon_i.d_data[31:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_sink No No No INPUT
tl_clkmgr_aon_i.d_source[0] No No Yes T32,T323,T324 INPUT
tl_clkmgr_aon_i.d_source[1] Yes Yes *T2,*T3,*T21 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_source[5:2] No No No INPUT
tl_clkmgr_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_clkmgr_aon_i.d_size[0] No No No INPUT
tl_clkmgr_aon_i.d_size[1] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_clkmgr_aon_i.d_opcode[0] Yes Yes *T75,*T295,*T67 Yes T75,T295,T67 INPUT
tl_clkmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_clkmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_pinmux_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_pinmux_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_pinmux_aon_o.a_opcode[1] No No No OUTPUT
tl_pinmux_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_error No No No INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_user.rsp_intg[2] No No No INPUT
tl_pinmux_aon_i.d_user.rsp_intg[5:3] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_pinmux_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_sink No No No INPUT
tl_pinmux_aon_i.d_source[5:0] Yes Yes *T51,*T52,*T1 Yes T51,T52,T1 INPUT
tl_pinmux_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_pinmux_aon_i.d_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 INPUT
tl_pinmux_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pinmux_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pinmux_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_otp_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_otp_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_otp_ctrl__core_o.a_opcode[1] No No No OUTPUT
tl_otp_ctrl__core_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_error No No No INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_otp_ctrl__core_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_sink No No No INPUT
tl_otp_ctrl__core_i.d_source[1:0] Yes Yes *T6,*T32,*T56 Yes T6,T32,T56 INPUT
tl_otp_ctrl__core_i.d_source[5:2] No No No INPUT
tl_otp_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__core_i.d_size[0] No No No INPUT
tl_otp_ctrl__core_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__core_i.d_opcode[0] Yes Yes *T113,*T154,*T176 Yes T113,T154,T176 INPUT
tl_otp_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T51,T52 Yes T51,T52 OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0] Yes Yes T51,T52 Yes T51,T52 OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_otp_ctrl__prim_o.a_opcode[1] No No No OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_valid Yes Yes T51,T52 Yes T51,T52 OUTPUT
tl_otp_ctrl__prim_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_error Yes Yes T1,T2,T3 Yes T2,T3,T21 INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T51,T52 Yes T51,T52 INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[2:0] Yes Yes *T51,*T52,*T1 Yes T51,T52,T2 INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[3] No No No INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[5:4] Yes Yes *T51,*T52,*T2 Yes T51,T52,T1 INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6] No No No INPUT
tl_otp_ctrl__prim_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T2,T3,T21 INPUT
tl_otp_ctrl__prim_i.d_sink No No No INPUT
tl_otp_ctrl__prim_i.d_source[0] Yes Yes *T51,*T52 Yes T51,T52 INPUT
tl_otp_ctrl__prim_i.d_source[5:1] No No No INPUT
tl_otp_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__prim_i.d_size[0] No No No INPUT
tl_otp_ctrl__prim_i.d_size[1] Yes Yes T51,T52 Yes T51,T52 INPUT
tl_otp_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__prim_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T2,T3,T21 INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__prim_i.d_valid Yes Yes T51,T52 Yes T51,T52 INPUT
tl_lc_ctrl_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0] Yes Yes T62,T4,T28 Yes T62,T4,T28 OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.instr_type[2:1] No No No OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_data[31:0] Yes Yes T62,T4,T28 Yes T62,T4,T28 OUTPUT
tl_lc_ctrl_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_lc_ctrl_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_lc_ctrl_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_lc_ctrl_o.a_opcode[1] No No No OUTPUT
tl_lc_ctrl_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_valid Yes Yes T62,T4,T28 Yes T62,T4,T28 OUTPUT
tl_lc_ctrl_i.a_ready Yes Yes T62,T4,T28 Yes T62,T4,T28 INPUT
tl_lc_ctrl_i.d_error No No No INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0] Yes Yes T4,T28,T5 Yes T62,T4,T28 INPUT
tl_lc_ctrl_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T207 Yes T4,T5,T53 INPUT
tl_lc_ctrl_i.d_user.rsp_intg[3:2] No No No INPUT
tl_lc_ctrl_i.d_user.rsp_intg[5:4] Yes Yes T62,T4,T5 Yes T62,T4,T28 INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6] No No No INPUT
tl_lc_ctrl_i.d_data[31:0] Yes Yes T62,T4,T28 Yes T62,T4,T28 INPUT
tl_lc_ctrl_i.d_sink No No No INPUT
tl_lc_ctrl_i.d_source[1:0] Yes Yes *T29,*T30,*T34 Yes T29,T30,T34 INPUT
tl_lc_ctrl_i.d_source[5:2] No No No INPUT
tl_lc_ctrl_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_lc_ctrl_i.d_size[0] No No No INPUT
tl_lc_ctrl_i.d_size[1] Yes Yes T62,T4,T5 Yes T62,T4,T28 INPUT
tl_lc_ctrl_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_lc_ctrl_i.d_opcode[0] Yes Yes *T62,*T4,*T5 Yes T62,T4,T28 INPUT
tl_lc_ctrl_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_lc_ctrl_i.d_valid Yes Yes T62,T4,T28 Yes T62,T4,T28 INPUT
tl_sensor_ctrl_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[1] No No No OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_error No No No INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T98,T125,T126 Yes T98,T125,T126 INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[1:0] Yes Yes T98,T125,T126 Yes T53,T98,T125 INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[5:4] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_sensor_ctrl_aon_i.d_data[31:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_sink No No No INPUT
tl_sensor_ctrl_aon_i.d_source[1:0] Yes Yes *T51,*T2,*T3 Yes T51,T1,T2 INPUT
tl_sensor_ctrl_aon_i.d_source[5:2] No No No INPUT
tl_sensor_ctrl_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sensor_ctrl_aon_i.d_size[0] No No No INPUT
tl_sensor_ctrl_aon_i.d_size[1] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sensor_ctrl_aon_i.d_opcode[0] Yes Yes *T2,*T3,*T21 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sensor_ctrl_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0] Yes Yes T21,T59,T62 Yes T21,T59,T62 OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.instr_type[2:1] No No No OUTPUT
tl_alert_handler_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_data[31:0] Yes Yes T21,T59,T62 Yes T21,T59,T62 OUTPUT
tl_alert_handler_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_alert_handler_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_alert_handler_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_alert_handler_o.a_opcode[1] No No No OUTPUT
tl_alert_handler_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_valid Yes Yes T21,T59,T62 Yes T21,T59,T62 OUTPUT
tl_alert_handler_i.a_ready Yes Yes T21,T59,T62 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_error No No No INPUT
tl_alert_handler_i.d_user.data_intg[6:0] Yes Yes T21,T59,T62 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_user.rsp_intg[1:0] Yes Yes T21,T59,T62 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_user.rsp_intg[3:2] No No No INPUT
tl_alert_handler_i.d_user.rsp_intg[5:4] Yes Yes T21,T62,T63 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_user.rsp_intg[6] No No No INPUT
tl_alert_handler_i.d_data[31:0] Yes Yes T21,T59,T62 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_sink No No No INPUT
tl_alert_handler_i.d_source[0] No No No INPUT
tl_alert_handler_i.d_source[1] Yes Yes *T21,*T59,*T62 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_source[5:2] No No No INPUT
tl_alert_handler_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_alert_handler_i.d_size[0] No No No INPUT
tl_alert_handler_i.d_size[1] Yes Yes T21,T62,T63 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_alert_handler_i.d_opcode[0] Yes Yes *T21,*T59,*T62 Yes T21,T59,T62 INPUT
tl_alert_handler_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_alert_handler_i.d_valid Yes Yes T21,T59,T62 Yes T21,T59,T62 INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0] Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0] Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid Yes Yes T60,T28,T6 Yes T60,T28,T6 OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error No No No INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[5:0] Yes Yes T60,T190,*T105 Yes T60,T190,T105 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6] No No No INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[1:0] Yes Yes T60,T25,T26 Yes T60,T28,T6 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[5:4] Yes Yes T60,*T25,*T26 Yes T60,T28,T6 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0] Yes Yes T60,T25,T26 Yes T60,T28,T6 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink No No No INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[1:0] Yes Yes *T51,*T60,*T26 Yes T51,T60,T28 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1] Yes Yes T60,T25,T26 Yes T60,T28,T6 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0] Yes Yes *T60,*T190,*T105 Yes T60,T170,T82 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid Yes Yes T60,T28,T6 Yes T60,T28,T6 INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error Yes Yes T1,T2,T3 Yes T2,T3,T21 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[2:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink No No No INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[1:0] Yes Yes *T35,*T167,*T141 Yes T35,T167,T141 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_data[31:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
tl_aon_timer_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_aon_timer_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_aon_timer_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_aon_timer_aon_o.a_opcode[1] No No No OUTPUT
tl_aon_timer_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_valid Yes Yes T2,T3,T21 Yes T2,T3,T21 OUTPUT
tl_aon_timer_aon_i.a_ready Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_error No No No INPUT
tl_aon_timer_aon_i.d_user.data_intg[0] Yes Yes *T2,*T3,*T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_user.data_intg[1] No Yes *T308,*T309,*T310 No INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:2] Yes Yes T3,T311,T312 Yes T3,T311,T312 INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[1:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[5:4] Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_aon_timer_aon_i.d_data[31:0] Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_sink No No No INPUT
tl_aon_timer_aon_i.d_source[0] No No No INPUT
tl_aon_timer_aon_i.d_source[1] Yes Yes *T2,*T3,*T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_source[5:2] No No No INPUT
tl_aon_timer_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aon_timer_aon_i.d_size[0] No No No INPUT
tl_aon_timer_aon_i.d_size[1] Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aon_timer_aon_i.d_opcode[0] Yes Yes *T2,*T3,*T21 Yes T2,T3,T21 INPUT
tl_aon_timer_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aon_timer_aon_i.d_valid Yes Yes T2,T3,T21 Yes T2,T3,T21 INPUT
tl_sysrst_ctrl_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T99,T17,T18 Yes T99,T17,T18 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0] Yes Yes T99,T17,T18 Yes T99,T17,T18 OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[1] No No No OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_valid Yes Yes T99,T17,T18 Yes T99,T17,T18 OUTPUT
tl_sysrst_ctrl_aon_i.a_ready Yes Yes T99,T17,T18 Yes T99,T17,T18 INPUT
tl_sysrst_ctrl_aon_i.d_error No No No INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T99,T17,T18 Yes T99,T17,T18 INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[1:0] Yes Yes T99,T17,T18 Yes T99,T17,T18 INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[5:4] Yes Yes T18,T325,T139 Yes T99,T17,T18 INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0] Yes Yes T99,T17,T18 Yes T99,T17,T18 INPUT
tl_sysrst_ctrl_aon_i.d_sink No No No INPUT
tl_sysrst_ctrl_aon_i.d_source[1:0] Yes Yes *T51,*T99,*T17 Yes T51,T99,T17 INPUT
tl_sysrst_ctrl_aon_i.d_source[5:2] No No No INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sysrst_ctrl_aon_i.d_size[0] No No No INPUT
tl_sysrst_ctrl_aon_i.d_size[1] Yes Yes T18,T325,T139 Yes T99,T17,T18 INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0] Yes Yes *T99,*T17,*T18 Yes T99,T17,T18 INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sysrst_ctrl_aon_i.d_valid Yes Yes T99,T17,T18 Yes T99,T17,T18 INPUT
tl_adc_ctrl_aon_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T100,T110,T16 Yes T100,T110,T16 OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[2:1] No No No OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0] Yes Yes T100,T110,T16 Yes T100,T110,T16 OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_adc_ctrl_aon_o.a_opcode[1] No No No OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_valid Yes Yes T100,T53,T110 Yes T100,T53,T110 OUTPUT
tl_adc_ctrl_aon_i.a_ready Yes Yes T100,T53,T110 Yes T100,T53,T110 INPUT
tl_adc_ctrl_aon_i.d_error No No No INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[4:0] Yes Yes T100,*T16,*T41 Yes T100,T16,T31 INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[5] No Yes *T100,*T31,*T42 No INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6] Yes Yes T100,T326,T327 Yes T100,T326,T327 INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[1:0] Yes Yes T100,T110,T16 Yes T100,T53,T110 INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[3:2] No No No INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[5:4] Yes Yes T31,T42,T43 Yes T100,T53,T110 INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6] No No No INPUT
tl_adc_ctrl_aon_i.d_data[31:0] Yes Yes T100,T110,T16 Yes T100,T53,T110 INPUT
tl_adc_ctrl_aon_i.d_sink No No No INPUT
tl_adc_ctrl_aon_i.d_source[0] No No No INPUT
tl_adc_ctrl_aon_i.d_source[1] Yes Yes *T100,*T110,*T16 Yes T100,T110,T16 INPUT
tl_adc_ctrl_aon_i.d_source[5:2] No No No INPUT
tl_adc_ctrl_aon_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_adc_ctrl_aon_i.d_size[0] No No No INPUT
tl_adc_ctrl_aon_i.d_size[1] Yes Yes T31,T42,T43 Yes T100,T53,T110 INPUT
tl_adc_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_adc_ctrl_aon_i.d_opcode[0] Yes Yes *T100,*T110,*T16 Yes T100,T110,T16 INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_adc_ctrl_aon_i.d_valid Yes Yes T100,T53,T110 Yes T100,T53,T110 INPUT
tl_ast_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.instr_type[2:1] No No No OUTPUT
tl_ast_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_source[5:0] Yes Yes *T29,*T6,*T30 Yes T29,T6,T30 OUTPUT
tl_ast_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_size[1:0] Yes Yes T14,T15,T20 Yes T14,T15,T20 OUTPUT
tl_ast_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_opcode[0] Yes Yes *T14,*T15,*T20 Yes T14,T15,T20 OUTPUT
tl_ast_o.a_opcode[1] No No No OUTPUT
tl_ast_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_error No No No INPUT
tl_ast_i.d_user.data_intg[6:0] No No No INPUT
tl_ast_i.d_user.rsp_intg[1:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_ast_i.d_user.rsp_intg[3:2] No No No INPUT
tl_ast_i.d_user.rsp_intg[4] Yes Yes *T2,*T3,*T21 Yes T1,T2,T3 INPUT
tl_ast_i.d_user.rsp_intg[6:5] No No No INPUT
tl_ast_i.d_data[31:0] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_ast_i.d_sink No No No INPUT
tl_ast_i.d_source[0] No No No INPUT
tl_ast_i.d_source[5:1] Yes Yes T14,*T15,T23 Yes T14,T15,T23 INPUT
tl_ast_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_ast_i.d_size[0] No No No INPUT
tl_ast_i.d_size[1] Yes Yes T2,T3,T21 Yes T1,T2,T3 INPUT
tl_ast_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_ast_i.d_opcode[0] No No No INPUT
tl_ast_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_ast_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%