Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T192,T193,T228
0	1	Covered	T192,T193,T228
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T192,T193,T228
1	Covered	T192,T193,T228

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T192,T193,T228
1	Covered	T192,T193,T228

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T192,T193,T228
1	1	Covered	T192,T193,T228

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T192,T193,T228
1	0	Covered	T192,T193,T228
1	1	Covered	T192,T193,T228

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T192,T193,T228

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T192,T193,T228
0	Covered	T192,T193,T228

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T192,T193,T228
0	Covered	T192,T193,T228

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	750741610	731464714	0	0
CheckNGreaterZero_A	1918	1918	0	0
GntImpliesReady_A	750741610	5522	0	0
GntImpliesValid_A	750741610	5522	0	0
GrantKnown_A	750741610	731464714	0	0
IdxKnown_A	750741610	731464714	0	0
IndexIsCorrect_A	750741610	5522	0	0
NoReadyValidNoGrant_A	750741610	0	0	0
Priority_A	750741610	5522	0	0
ReadyAndValidImplyGrant_A	750741610	5522	0	0
ReqAndReadyImplyGrant_A	750741610	5522	0	0
ReqImpliesValid_A	750741610	5522	0	0
ValidKnown_A	750741610	731464714	0	0
gen_data_port_assertion.DataFlow_A	750741610	5522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	731464714	0	0
T1	439106	438996	0	0
T2	423676	423348	0	0
T3	363312	363078	0	0
T4	323400	323058	0	0
T21	504696	504464	0	0
T50	304064	304054	0	0
T59	325014	324904	0	0
T62	562080	561854	0	0
T74	662006	661904	0	0
T75	1296006	1295444	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1918	1918	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T21	2	2	0	0
T50	2	2	0	0
T59	2	2	0	0
T62	2	2	0	0
T74	2	2	0	0
T75	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	731464714	0	0
T1	439106	438996	0	0
T2	423676	423348	0	0
T3	363312	363078	0	0
T4	323400	323058	0	0
T21	504696	504464	0	0
T50	304064	304054	0	0
T59	325014	324904	0	0
T62	562080	561854	0	0
T74	662006	661904	0	0
T75	1296006	1295444	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	731464714	0	0
T1	439106	438996	0	0
T2	423676	423348	0	0
T3	363312	363078	0	0
T4	323400	323058	0	0
T21	504696	504464	0	0
T50	304064	304054	0	0
T59	325014	324904	0	0
T62	562080	561854	0	0
T74	662006	661904	0	0
T75	1296006	1295444	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	731464714	0	0
T1	439106	438996	0	0
T2	423676	423348	0	0
T3	363312	363078	0	0
T4	323400	323058	0	0
T21	504696	504464	0	0
T50	304064	304054	0	0
T59	325014	324904	0	0
T62	562080	561854	0	0
T74	662006	661904	0	0
T75	1296006	1295444	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750741610	5522	0	0
T145	130696	0	0	0
T192	164914	1846	0	0
T193	167242	1842	0	0
T228	0	1834	0	0
T266	277716	0	0	0
T322	160050	0	0	0
T384	1897068	0	0	0
T385	301512	0	0	0
T386	382082	0	0	0
T387	321472	0	0	0
T388	120558	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T192,T193,T228
0	1	Covered	T192,T193,T228
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T192,T193,T228
1	Covered	T192,T193,T228

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T192,T193,T228
1	Covered	T192,T193,T228

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T192,T193,T228
1	1	Covered	T192,T193,T228

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T192,T193,T228
1	0	Covered	T192,T193,T228
1	1	Covered	T192,T193,T228

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T192,T193,T228

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T192,T193,T228
0	Covered	T192,T193,T228

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T192,T193,T228
0	Covered	T192,T193,T228

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375370805	365732357	0	0
CheckNGreaterZero_A	959	959	0	0
GntImpliesReady_A	375370805	4490	0	0
GntImpliesValid_A	375370805	4490	0	0
GrantKnown_A	375370805	365732357	0	0
IdxKnown_A	375370805	365732357	0	0
IndexIsCorrect_A	375370805	4490	0	0
NoReadyValidNoGrant_A	375370805	0	0	0
Priority_A	375370805	4490	0	0
ReadyAndValidImplyGrant_A	375370805	4490	0	0
ReqAndReadyImplyGrant_A	375370805	4490	0	0
ReqImpliesValid_A	375370805	4490	0	0
ValidKnown_A	375370805	365732357	0	0
gen_data_port_assertion.DataFlow_A	375370805	4490	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	4490	0	0
T145	65348	0	0	0
T192	82457	1502	0	0
T193	83621	1498	0	0
T228	0	1490	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T192,T193,T228
0	1	Covered	T192,T193,T228
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T192,T193,T228
1	Covered	T192,T193,T228

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T192,T193,T228
1	Covered	T192,T193,T228

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T192,T193,T228
1	1	Covered	T192,T193,T228

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T192,T193,T228
1	0	Covered	T192,T193,T228
1	1	Covered	T192,T193,T228

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T192,T193,T228

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T192,T193,T228
0	Covered	T192,T193,T228

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T192,T193,T228
0	Covered	T192,T193,T228

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	375370805	365732357	0	0
CheckNGreaterZero_A	959	959	0	0
GntImpliesReady_A	375370805	1032	0	0
GntImpliesValid_A	375370805	1032	0	0
GrantKnown_A	375370805	365732357	0	0
IdxKnown_A	375370805	365732357	0	0
IndexIsCorrect_A	375370805	1032	0	0
NoReadyValidNoGrant_A	375370805	0	0	0
Priority_A	375370805	1032	0	0
ReadyAndValidImplyGrant_A	375370805	1032	0	0
ReqAndReadyImplyGrant_A	375370805	1032	0	0
ReqImpliesValid_A	375370805	1032	0	0
ValidKnown_A	375370805	365732357	0	0
gen_data_port_assertion.DataFlow_A	375370805	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T21	1	1	0	0
T50	1	1	0	0
T59	1	1	0	0
T62	1	1	0	0
T74	1	1	0	0
T75	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	365732357	0	0
T1	219553	219498	0	0
T2	211838	211674	0	0
T3	181656	181539	0	0
T4	161700	161529	0	0
T21	252348	252232	0	0
T50	152032	152027	0	0
T59	162507	162452	0	0
T62	281040	280927	0	0
T74	331003	330952	0	0
T75	648003	647722	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375370805	1032	0	0
T145	65348	0	0	0
T192	82457	344	0	0
T193	83621	344	0	0
T228	0	344	0	0
T266	138858	0	0	0
T322	80025	0	0	0
T384	948534	0	0	0
T385	150756	0	0	0
T386	191041	0	0	0
T387	160736	0	0	0
T388	60279	0	0	0