Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.25	100.00	89.01			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc	95.45	90.91	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc	95.45	90.91	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc	98.08	100.00	92.31			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc	98.08	100.00	92.31			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc	98.08	100.00	92.31			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=10,ResetVal=0,BitMask=769,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

SCORE	COND
95.45	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

SCORE	COND
95.45	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

SCORE	COND
96.43	85.71

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T40,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T40,T31
1	1	Covered	T16,T40,T31

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T40,T41
1	0	Covered	T16,T40,T31

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T40,T31
1	1	Covered	T16,T40,T31

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T40,T41

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T40,T41

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T40,T41
1	1	Covered	T16,T40,T41

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T16,T40,T41
1	-	Covered	T16,T40,T41

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T40,T41

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T40,T41
1	1	Covered	T16,T40,T41

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T40,T31
0	0	1	Covered	T16,T40,T31
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T40,T31
0	0	1	Covered	T16,T40,T31
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	35364	0	0
DstReqKnown_A	31376300	27000875	0	0
SrcAckBusyChk_A	2147483647	90	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35364	0	0
T16	331028	3514	0	0
T19	541350	0	0	0
T31	0	404	0	0
T40	31689	1368	0	0
T41	0	1850	0	0
T42	0	276	0	0
T43	0	443	0	0
T44	27618	1468	0	0
T45	0	898	0	0
T46	0	1299	0	0
T47	0	1484	0	0
T48	0	4289	0	0
T49	0	4430	0	0
T58	0	1496	0	0
T86	0	1755	0	0
T87	0	1879	0	0
T88	0	1765	0	0
T89	73548	0	0	0
T90	44236	0	0	0
T91	65786	0	0	0
T92	382572	0	0	0
T93	424696	0	0	0
T94	463656	0	0	0
T95	328870	0	0	0
T96	165218	0	0	0
T104	55410	0	0	0
T362	30535	0	0	0
T404	0	1967	0	0
T405	0	1879	0	0
T406	17964	0	0	0
T407	87778	0	0	0
T408	37174	0	0	0
T409	59132	0	0	0
T410	39493	0	0	0
T411	183887	0	0	0
T412	26533	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31376300	27000875	0	0
T1	15200	13625	0	0
T2	21200	17125	0	0
T3	20350	16225	0	0
T4	22250	15125	0	0
T21	20550	16450	0	0
T50	80725	76675	0	0
T59	16150	12100	0	0
T62	23125	19050	0	0
T74	22075	18025	0	0
T75	60800	56625	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	90	0	0
T16	331028	10	0	0
T19	541350	0	0	0
T31	0	1	0	0
T40	31689	3	0	0
T41	0	5	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	27618	4	0	0
T45	0	3	0	0
T46	0	3	0	0
T47	0	3	0	0
T48	0	10	0	0
T49	0	10	0	0
T58	0	3	0	0
T86	0	5	0	0
T87	0	5	0	0
T88	0	5	0	0
T89	73548	0	0	0
T90	44236	0	0	0
T91	65786	0	0	0
T92	382572	0	0	0
T93	424696	0	0	0
T94	463656	0	0	0
T95	328870	0	0	0
T96	165218	0	0	0
T104	55410	0	0	0
T362	30535	0	0	0
T404	0	5	0	0
T405	0	5	0	0
T406	17964	0	0	0
T407	87778	0	0	0
T408	37174	0	0	0
T409	59132	0	0	0
T410	39493	0	0	0
T411	183887	0	0	0
T412	26533	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1336450	1326600	0	0
T2	1312100	1299275	0	0
T3	1119225	1108650	0	0
T4	1063650	1029200	0	0
T21	1544650	1532575	0	0
T50	9149150	9131750	0	0
T59	1091375	1081250	0	0
T62	1718425	1704775	0	0
T74	2008725	1995350	0	0
T75	3945275	3935300	0	0