Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143508	1			T35	17		T36	28		T37	105
values[2]	10236	1			T36	1		T37	1		T50	1
values[3]	3566	1			T259	45		T434	1		T640	9
values[4]	2094	1			T259	15		T434	1		T640	6
values[5]	1230	1			T259	12		T434	1		T640	6
values[6]	864	1			T259	2		T434	1		T640	10
values[7]	645	1			T434	1		T640	13		T456	6
values[8]	498	1			T434	1		T640	5		T456	7
values[9]	455	1			T434	1		T640	9		T456	6
values[10]	378	1			T434	1		T640	4		T456	7
values[11]	389	1			T434	1		T640	13		T456	6
values[12]	359	1			T434	1		T640	11		T456	11
values[13]	342	1			T434	1		T640	6		T456	10
values[14]	274	1			T434	1		T640	10		T456	2
values[15]	282	1			T434	1		T640	7		T456	6
values[16]	289	1			T434	1		T640	6		T456	5
values[17]	292	1			T434	1		T640	11		T456	3
values[18]	302	1			T434	1		T640	8		T456	6
values[19]	243	1			T434	1		T640	6		T456	8
values[20]	241	1			T434	1		T640	8		T456	17
values[21]	282	1			T434	1		T640	6		T456	14
values[22]	292	1			T434	1		T640	3		T456	5
values[23]	268	1			T434	1		T640	6		T456	3
values[24]	268	1			T434	1		T640	9		T456	7
values[25]	245	1			T434	1		T640	8		T456	4
values[26]	235	1			T434	1		T640	8		T456	3
values[27]	306	1			T434	1		T640	14		T456	13
values[28]	284	1			T434	1		T640	5		T456	16
values[29]	234	1			T434	1		T640	9		T456	6
values[30]	259	1			T434	1		T640	7		T456	6
values[31]	291	1			T434	1		T640	4		T456	10
values[32]	213	1			T434	1		T640	5		T456	4
values[33]	252	1			T434	1		T640	15		T456	3
values[34]	241	1			T434	1		T640	13		T456	6
values[35]	259	1			T434	1		T640	13		T456	10
values[36]	249	1			T434	1		T640	6		T456	10
values[37]	289	1			T434	1		T640	7		T456	3
values[38]	257	1			T434	1		T640	8		T456	14
values[39]	221	1			T434	1		T640	7		T456	9
values[40]	233	1			T434	1		T456	10		T700	5
values[41]	231	1			T434	1		T456	5		T700	8
values[42]	222	1			T434	1		T456	7		T700	7
values[43]	266	1			T434	1		T456	9		T700	13
values[44]	248	1			T434	1		T456	3		T700	5
values[45]	236	1			T434	1		T456	7		T700	7
values[46]	195	1			T434	1		T456	5		T700	18
values[47]	200	1			T434	1		T456	6		T700	7
values[48]	219	1			T434	1		T456	4		T700	1
values[49]	200	1			T434	1		T456	2		T805	1
values[50]	206	1			T434	1		T456	10		T805	1
values[51]	209	1			T434	1		T456	2		T805	1
values[52]	203	1			T434	1		T456	5		T805	1
values[53]	259	1			T434	1		T456	15		T805	1
values[54]	216	1			T434	1		T456	7		T805	1
values[55]	224	1			T434	1		T456	21		T805	1
values[56]	212	1			T434	1		T456	16		T805	1
values[57]	168	1			T434	1		T456	3		T805	1
values[58]	194	1			T434	1		T456	3		T805	1
values[59]	158	1			T434	2		T456	3		T805	1
values[60]	176	1			T434	1		T456	5		T805	1
values[61]	244	1			T434	1		T456	6		T805	1
values[62]	188	1			T434	1		T456	3		T805	1
values[63]	185	1			T434	1		T456	9		T805	1
values[64]	171	1			T434	1		T456	7		T805	1
values[65]	163	1			T434	1		T456	5		T805	1
values[66]	204	1			T434	1		T456	12		T805	1
values[67]	135	1			T434	1		T456	4		T805	1
values[68]	127	1			T434	1		T456	3		T805	1
values[69]	99	1			T434	1		T456	5		T805	1
values[70]	91	1			T434	1		T456	5		T805	1
values[71]	66	1			T434	1		T456	8		T805	1
values[72]	87	1			T434	1		T456	14		T805	1
values[73]	67	1			T434	1		T805	1		T450	1
values[74]	69	1			T434	1		T805	1		T450	1
values[75]	78	1			T434	1		T805	1		T450	1
values[76]	78	1			T434	1		T805	1		T450	1
values[77]	55	1			T434	1		T805	1		T450	1
values[78]	59	1			T434	1		T805	1		T450	1
values[79]	46	1			T434	1		T805	1		T450	1
values[80]	63	1			T434	2		T805	1		T450	1
values[81]	76	1			T434	1		T805	1		T450	1
values[82]	49	1			T434	1		T805	1		T450	2
values[83]	41	1			T434	1		T805	1		T450	1
values[84]	56	1			T434	1		T805	1		T450	1
values[85]	30	1			T434	2		T805	1		T450	1
values[86]	34	1			T434	1		T805	1		T450	1
values[87]	39	1			T434	1		T805	1		T450	1
values[88]	42	1			T434	1		T805	1		T450	1
values[89]	41	1			T434	1		T805	1		T450	1
values[90]	39	1			T434	1		T805	1		T450	1
values[91]	34	1			T434	1		T805	1		T450	1
values[92]	24	1			T434	1		T805	1		T450	1
values[93]	31	1			T434	5		T805	1		T450	1
values[94]	36	1			T434	3		T805	1		T450	1
values[95]	45	1			T434	8		T805	1		T450	1
values[96]	42	1			T434	3		T805	2		T450	1
values[97]	34	1			T434	2		T805	1		T450	1
values[98]	41	1			T434	5		T805	1		T450	1
values[99]	37	1			T434	2		T805	1		T450	1
values[100]	48	1			T434	7		T805	3		T450	1
values[101]	52	1			T434	4		T805	3		T450	1
values[102]	50	1			T434	4		T805	6		T450	1
values[103]	39	1			T434	2		T805	1		T450	1
values[104]	50	1			T434	2		T805	5		T450	1
values[105]	43	1			T434	4		T805	5		T450	1
values[106]	47	1			T434	1		T805	4		T450	1
values[107]	40	1			T434	2		T805	1		T450	1
values[108]	42	1			T434	2		T805	1		T450	1
values[109]	45	1			T434	4		T805	1		T450	1
values[110]	45	1			T434	4		T805	1		T450	1
values[111]	45	1			T434	2		T805	1		T450	1
values[112]	47	1			T434	3		T805	2		T450	1
values[113]	39	1			T434	3		T805	2		T450	1
values[114]	41	1			T434	1		T805	1		T450	1
values[115]	36	1			T434	1		T805	4		T450	1
values[116]	33	1			T434	1		T805	2		T450	2
values[117]	37	1			T434	1		T805	1		T450	1
values[118]	46	1			T434	3		T805	2		T450	1
values[119]	47	1			T434	3		T805	1		T450	1
values[120]	32	1			T434	1		T805	1		T450	3
values[121]	43	1			T434	3		T805	2		T450	4
values[122]	30	1			T434	2		T805	1		T450	3
values[123]	38	1			T434	1		T805	2		T450	2
values[124]	43	1			T434	7		T805	3		T450	2
values[125]	44	1			T434	2		T805	3		T450	3
values[126]	75	1			T434	3		T805	6		T450	2
values[127]	463	1			T434	33		T805	34		T450	42
values[128]	3978	1			T434	304		T805	297		T450	389