Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.37	95.45	94.67	95.51		95.45	97.57	99.58

Total tests in report: 2875

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
28.09	28.09	28.56	28.56	26.00	26.00	21.17	21.17			45.75	45.75	43.52	43.52	3.57	3.57	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3456443508
53.91	25.82	69.71	41.15	60.11	34.11	54.38	33.21			65.74	19.99	49.26	5.74	24.27	20.69	/workspace/coverage/cover_reg_top/42.xbar_stress_all.186448094
69.17	15.26	81.41	11.71	78.28	18.17	61.45	7.07			83.67	17.94	85.93	36.67	24.27	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2760087121
72.61	3.44	81.41	0.00	78.60	0.32	61.45	0.00			83.81	0.13	85.93	0.00	44.47	20.20	/workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1173622708
75.65	3.04	83.34	1.93	79.12	0.53	71.57	10.12			84.27	0.47	91.11	5.19	44.48	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2289401076
77.91	2.26	83.34	0.00	79.12	0.00	71.57	0.00			84.27	0.00	91.11	0.00	58.04	13.56	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2329164370
79.72	1.81	83.34	0.00	79.20	0.07	71.57	0.00			84.27	0.00	91.11	0.00	68.81	10.78	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.218418411
81.52	1.80	88.75	5.41	81.53	2.33	71.90	0.33			87.00	2.73	91.11	0.00	68.81	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.981368724
83.05	1.53	88.77	0.02	82.06	0.53	72.68	0.78			87.08	0.08	91.11	0.00	76.59	7.78	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3830652745
84.39	1.34	88.87	0.09	82.13	0.07	80.19	7.51			87.25	0.18	91.30	0.19	76.59	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4096415303
85.46	1.07	89.73	0.87	84.83	2.70	80.21	0.03			90.08	2.83	91.30	0.00	76.59	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1406908671
86.38	0.92	89.73	0.00	84.83	0.00	85.74	5.52			90.08	0.00	91.30	0.00	76.59	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.815834211
87.28	0.90	89.73	0.00	84.83	0.00	85.74	0.00			90.08	0.00	91.30	0.00	81.99	5.39	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3188497465
88.16	0.88	90.51	0.78	85.02	0.19	85.76	0.02			90.31	0.23	95.37	4.07	81.99	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3529801735
88.91	0.76	90.51	0.00	85.23	0.21	85.76	0.00			90.32	0.01	95.37	0.00	86.30	4.31	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.4197743158
89.52	0.60	91.73	1.22	86.21	0.98	85.99	0.23			91.50	1.18	95.37	0.00	86.30	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3958107752
90.08	0.56	91.73	0.00	86.26	0.05	85.99	0.00			91.50	0.00	95.37	0.00	89.62	3.33	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3568095306
90.61	0.53	92.56	0.84	87.31	1.05	86.00	0.01			92.77	1.27	95.37	0.00	89.62	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.851706112
91.08	0.48	92.57	0.01	89.76	2.45	86.00	0.00			92.77	0.00	95.37	0.00	90.04	0.41	/workspace/coverage/cover_reg_top/3.chip_tl_errors.2518557783
91.56	0.47	93.21	0.63	90.30	0.54	86.32	0.31			93.38	0.62	96.11	0.74	90.04	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.222208046
91.92	0.36	93.21	0.00	90.36	0.07	86.32	0.00			93.38	0.00	96.11	0.00	92.13	2.09	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1578369704
92.26	0.34	93.21	0.00	90.49	0.12	86.32	0.00			93.38	0.00	96.11	0.00	94.07	1.94	/workspace/coverage/cover_reg_top/5.xbar_stress_all.1245162775
92.56	0.29	93.21	0.00	90.49	0.01	88.06	1.74			93.38	0.00	96.11	0.00	94.08	0.01	/workspace/coverage/default/83.chip_sw_all_escalation_resets.1083344786
92.85	0.29	93.22	0.01	90.49	0.01	89.79	1.73			93.38	0.00	96.11	0.00	94.08	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.649086994
93.09	0.24	93.72	0.50	90.93	0.44	89.89	0.10			93.81	0.43	96.11	0.00	94.08	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.4035493611
93.33	0.24	93.72	0.00	90.95	0.02	89.89	0.00			93.81	0.00	96.11	0.00	95.51	1.43	/workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.4052992083
93.55	0.22	93.92	0.21	91.47	0.52	89.90	0.01			94.36	0.55	96.11	0.00	95.56	0.05	/workspace/coverage/default/0.chip_jtag_csr_rw.2638438601
93.76	0.20	93.92	0.00	91.53	0.06	89.90	0.00			94.36	0.00	96.11	0.00	96.71	1.15	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.1766525595
93.93	0.17	94.21	0.29	91.86	0.33	90.33	0.43			94.36	0.00	96.11	0.00	96.71	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2206961865
94.09	0.16	94.21	0.00	91.87	0.01	90.46	0.13			94.36	0.00	96.11	0.00	97.56	0.85	/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.596636245
94.23	0.14	94.27	0.06	91.90	0.03	91.15	0.69			94.38	0.02	96.11	0.00	97.57	0.01	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.462096618
94.36	0.13	94.51	0.24	92.11	0.21	91.15	0.00			94.70	0.33	96.11	0.00	97.57	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2572393311
94.47	0.11	94.51	0.00	92.11	0.00	91.82	0.67			94.70	0.00	96.11	0.00	97.57	0.00	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3387360865
94.58	0.11	94.51	0.00	92.42	0.31	91.82	0.00			95.05	0.35	96.11	0.00	97.57	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3215746065
94.68	0.10	94.51	0.00	92.42	0.00	92.45	0.63			95.05	0.00	96.11	0.00	97.57	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4010163059
94.78	0.09	94.51	0.00	92.42	0.00	93.00	0.55			95.05	0.00	96.11	0.00	97.57	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.615653621
94.86	0.08	94.51	0.00	92.42	0.00	93.29	0.29			95.05	0.00	96.30	0.19	97.57	0.00	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.539121416
94.93	0.07	94.51	0.00	92.85	0.43	93.29	0.00			95.05	0.00	96.30	0.00	97.57	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1332501082
95.00	0.07	94.51	0.00	92.85	0.00	93.71	0.42			95.05	0.00	96.30	0.00	97.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2208020802
95.05	0.06	94.51	0.00	92.90	0.05	93.71	0.00			95.05	0.00	96.30	0.00	97.85	0.28	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2461677065
95.10	0.05	94.59	0.08	93.04	0.14	93.71	0.00			95.14	0.08	96.30	0.00	97.85	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2373467753
95.15	0.05	94.66	0.08	93.04	0.00	93.89	0.19			95.14	0.01	96.30	0.00	97.85	0.00	/workspace/coverage/default/4.chip_tap_straps_testunlock0.2951785623
95.19	0.04	94.70	0.03	93.05	0.01	93.90	0.01			95.15	0.01	96.48	0.19	97.86	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.1556584701
95.23	0.04	94.71	0.01	93.06	0.01	93.90	0.00			95.18	0.03	96.67	0.19	97.87	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864398725
95.27	0.04	94.71	0.00	93.11	0.05	93.90	0.00			95.18	0.00	96.67	0.00	98.06	0.19	/workspace/coverage/cover_reg_top/76.xbar_stress_all.903852922
95.31	0.04	94.71	0.01	93.12	0.01	93.94	0.04			95.18	0.00	96.85	0.19	98.06	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1791660051
95.35	0.04	94.72	0.01	93.13	0.01	93.94	0.00			95.19	0.01	97.04	0.19	98.07	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1478970420
95.39	0.04	94.72	0.01	93.14	0.01	93.95	0.01			95.19	0.01	97.22	0.19	98.08	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3593668663
95.42	0.04	94.72	0.01	93.16	0.01	93.96	0.01			95.20	0.01	97.41	0.19	98.10	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.1588993973
95.46	0.04	94.76	0.03	93.33	0.18	93.96	0.00			95.20	0.00	97.41	0.00	98.11	0.01	/workspace/coverage/cover_reg_top/21.chip_tl_errors.2809889036
95.50	0.04	94.76	0.00	93.33	0.00	94.17	0.22			95.20	0.00	97.41	0.00	98.11	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3267150307
95.53	0.03	94.76	0.00	93.34	0.01	94.17	0.00			95.20	0.00	97.41	0.00	98.30	0.19	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1949049893
95.56	0.03	94.76	0.00	93.35	0.01	94.18	0.01			95.20	0.00	97.59	0.19	98.30	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3518415827
95.59	0.03	94.76	0.00	93.43	0.09	94.18	0.00			95.30	0.10	97.59	0.00	98.30	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4251165855
95.62	0.03	94.76	0.00	93.43	0.00	94.35	0.17			95.30	0.00	97.59	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.72646735
95.65	0.03	94.76	0.00	93.43	0.00	94.51	0.16			95.30	0.00	97.59	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.2031418819
95.68	0.03	94.76	0.00	93.43	0.00	94.67	0.16			95.30	0.00	97.59	0.00	98.30	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2813224709
95.70	0.03	94.76	0.00	93.59	0.16	94.67	0.00			95.30	0.00	97.59	0.00	98.30	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.4217667185
95.73	0.03	94.78	0.02	93.63	0.04	94.75	0.09			95.31	0.01	97.59	0.00	98.30	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1124562656
95.75	0.02	94.79	0.02	93.68	0.05	94.81	0.06			95.34	0.03	97.59	0.00	98.30	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1824283371
95.77	0.02	94.79	0.00	93.68	0.01	94.81	0.00			95.34	0.00	97.59	0.00	98.43	0.13	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1662756582
95.79	0.02	94.85	0.05	93.74	0.05	94.81	0.00			95.35	0.02	97.59	0.00	98.43	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1604651441
95.81	0.02	94.85	0.00	93.86	0.12	94.81	0.00			95.35	0.00	97.59	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.2107094941
95.83	0.02	94.85	0.00	93.86	0.00	94.92	0.11			95.35	0.00	97.59	0.00	98.43	0.00	/workspace/coverage/default/0.rom_raw_unlock.226110904
95.85	0.02	94.85	0.00	93.86	0.00	95.02	0.10			95.35	0.00	97.59	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1503279616
95.86	0.01	94.85	0.00	93.86	0.01	95.02	0.00			95.35	0.00	97.59	0.00	98.51	0.08	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1010005614
95.88	0.01	94.85	0.00	93.94	0.08	95.02	0.00			95.35	0.00	97.59	0.00	98.51	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2315330242
95.89	0.01	94.88	0.03	93.99	0.05	95.02	0.00			95.35	0.00	97.59	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_gpio.229111946
95.90	0.01	94.88	0.01	94.04	0.05	95.02	0.00			95.35	0.00	97.59	0.00	98.52	0.01	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3054312156
95.91	0.01	94.88	0.00	94.04	0.00	95.02	0.00			95.35	0.00	97.59	0.00	98.59	0.07	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1390823279
95.93	0.01	94.88	0.00	94.04	0.00	95.02	0.00			95.35	0.00	97.59	0.00	98.66	0.07	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3689760211
95.94	0.01	94.90	0.01	94.06	0.02	95.04	0.02			95.37	0.02	97.59	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.944565295
95.95	0.01	94.93	0.04	94.08	0.02	95.04	0.00			95.38	0.01	97.59	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4012152809
95.96	0.01	94.97	0.04	94.10	0.02	95.04	0.00			95.39	0.01	97.59	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.387901403
95.97	0.01	94.97	0.00	94.17	0.06	95.04	0.00			95.39	0.00	97.59	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.806311511
95.98	0.01	94.99	0.02	94.20	0.03	95.05	0.01			95.39	0.00	97.59	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_alert_test.999491635
95.99	0.01	94.99	0.00	94.20	0.00	95.11	0.06			95.39	0.00	97.59	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_flash_init.1817903545
96.00	0.01	95.01	0.03	94.21	0.01	95.11	0.00			95.40	0.02	97.59	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1352157576
96.01	0.01	95.04	0.03	94.23	0.01	95.11	0.00			95.42	0.02	97.59	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3257069132
96.02	0.01	95.06	0.03	94.24	0.01	95.11	0.00			95.44	0.02	97.59	0.00	98.66	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.606487482
96.03	0.01	95.09	0.03	94.24	0.00	95.13	0.02			95.44	0.00	97.59	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.4140132068
96.03	0.01	95.09	0.00	94.29	0.05	95.13	0.00			95.44	0.00	97.59	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2362771419
96.04	0.01	95.09	0.00	94.29	0.00	95.18	0.05			95.44	0.00	97.59	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.106941489
96.05	0.01	95.09	0.00	94.34	0.04	95.18	0.00			95.44	0.00	97.59	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.755106757
96.06	0.01	95.09	0.00	94.34	0.01	95.20	0.02			95.44	0.00	97.59	0.00	98.67	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.1839297239
96.06	0.01	95.09	0.00	94.38	0.04	95.20	0.00			95.44	0.00	97.59	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2181568230
96.07	0.01	95.09	0.00	94.38	0.00	95.20	0.00			95.44	0.00	97.59	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.3173246088
96.07	0.01	95.09	0.00	94.41	0.03	95.20	0.00			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3901774711
96.08	0.01	95.12	0.02	94.41	0.00	95.21	0.01			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3852162548
96.08	0.01	95.12	0.01	94.44	0.03	95.21	0.00			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.274997684
96.09	0.01	95.13	0.01	94.45	0.01	95.22	0.01			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx.4024021342
96.09	0.01	95.13	0.00	94.45	0.00	95.25	0.03			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4225300657
96.10	0.01	95.13	0.00	94.45	0.00	95.28	0.03			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1854805875
96.10	0.01	95.13	0.00	94.45	0.00	95.30	0.03			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3755926534
96.11	0.01	95.15	0.01	94.45	0.00	95.31	0.01			95.44	0.00	97.59	0.00	98.71	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.631812879
96.11	0.01	95.15	0.00	94.45	0.00	95.31	0.00			95.44	0.00	97.59	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1674823084
96.12	0.01	95.15	0.00	94.45	0.00	95.31	0.00			95.44	0.00	97.59	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1610538105
96.12	0.01	95.15	0.00	94.45	0.00	95.31	0.00			95.44	0.00	97.59	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3325881870
96.12	0.01	95.15	0.00	94.46	0.01	95.33	0.01			95.44	0.00	97.59	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.692211080
96.13	0.01	95.15	0.00	94.46	0.01	95.33	0.01			95.44	0.00	97.59	0.00	98.79	0.01	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3173800964
96.13	0.01	95.15	0.00	94.49	0.02	95.33	0.00			95.44	0.00	97.59	0.00	98.79	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2537609475
96.13	0.01	95.15	0.00	94.49	0.00	95.34	0.01			95.44	0.00	97.59	0.00	98.80	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.56598231
96.14	0.01	95.15	0.00	94.49	0.00	95.36	0.02			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1229788019
96.14	0.01	95.15	0.00	94.49	0.00	95.38	0.02			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1065886192
96.14	0.01	95.15	0.00	94.51	0.02	95.38	0.00			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.784505202
96.15	0.01	95.15	0.00	94.52	0.02	95.38	0.00			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1013573894
96.15	0.01	95.15	0.00	94.54	0.02	95.38	0.00			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1278940540
96.15	0.01	95.16	0.01	94.54	0.00	95.38	0.01			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1717266324
96.15	0.01	95.17	0.01	94.54	0.00	95.38	0.01			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.1433395437
96.16	0.01	95.17	0.00	94.54	0.00	95.40	0.02			95.44	0.00	97.59	0.00	98.80	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.675826449
96.16	0.01	95.17	0.00	94.55	0.01	95.40	0.00			95.44	0.00	97.59	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1219116900
96.16	0.01	95.17	0.00	94.55	0.00	95.41	0.01			95.44	0.00	97.59	0.00	98.81	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.772496348
96.16	0.01	95.17	0.00	94.55	0.01	95.42	0.01			95.44	0.00	97.59	0.00	98.81	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4122285972
96.17	0.01	95.18	0.01	94.55	0.00	95.43	0.01			95.44	0.00	97.59	0.00	98.81	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3552321271
96.17	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.82	0.01	/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.3428866177
96.17	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2527750995
96.17	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.85	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.2935582758
96.17	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.86	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3691329771
96.18	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.87	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.2896628383
96.18	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1613695144
96.18	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.90	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1417089536
96.18	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4009392561
96.18	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.709344628
96.19	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.93	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2710875567
96.19	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.3367866677
96.19	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.95	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119441124
96.19	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.97	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.4131729060
96.19	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.98	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1081541639
96.20	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	98.99	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3890040683
96.20	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.00	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1042009904
96.20	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.01	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1380843507
96.20	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.02	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830991466
96.20	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.04	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3355726577
96.21	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.05	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4211875645
96.21	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.06	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1860267446
96.21	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.07	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.4134692170
96.21	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.08	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303363442
96.21	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.10	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.580729250
96.22	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.11	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448545762
96.22	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.12	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2164141385
96.22	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.13	0.01	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1585488651
96.22	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.14	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1197538951
96.22	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.15	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1884281246
96.23	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.17	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3970784457
96.23	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.18	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1813953632
96.23	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.19	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2914518766
96.23	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.20	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3061256887
96.23	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.21	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3482867069
96.24	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.22	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.946163357
96.24	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.24	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.295822464
96.24	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.25	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.102848887
96.24	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.26	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.64739088
96.24	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.27	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2813024841
96.24	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.28	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596189522
96.25	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.29	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2091814838
96.25	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.31	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2133617463
96.25	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.32	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2576745271
96.25	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.33	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.2389503981
96.25	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.34	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2921950751
96.26	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.35	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.4162444071
96.26	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.37	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1321508994
96.26	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.38	0.01	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677031320
96.26	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.39	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3091054623
96.26	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.40	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3235088814
96.27	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.41	0.01	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3300019177
96.27	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.42	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3700543509
96.27	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.44	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3306236967
96.27	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.45	0.01	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4236053412
96.27	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.46	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3569121935
96.28	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.47	0.01	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857423701
96.28	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.48	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.2895908266
96.28	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.49	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2528687314
96.28	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.51	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2519564442
96.28	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.52	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.688145204
96.29	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.53	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.579274869
96.29	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.54	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4166491184
96.29	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.55	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1060027171
96.29	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.57	0.01	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099208915
96.29	0.01	95.18	0.00	94.55	0.00	95.43	0.00			95.44	0.00	97.59	0.00	99.58	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2344879143
96.30	0.01	95.18	0.00	94.56	0.01	95.43	0.00			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.374999429
96.30	0.01	95.18	0.00	94.57	0.01	95.43	0.00			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1400043134
96.30	0.01	95.18	0.01	94.58	0.01	95.43	0.00			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4281759403
96.30	0.01	95.19	0.01	94.59	0.01	95.43	0.00			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3705671907
96.30	0.01	95.19	0.01	94.59	0.00	95.44	0.01			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2294769152
96.30	0.01	95.19	0.00	94.59	0.00	95.45	0.01			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.715743079
96.31	0.01	95.19	0.00	94.59	0.00	95.46	0.01			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_init.2056457089
96.31	0.01	95.19	0.00	94.59	0.00	95.47	0.01			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.280193929
96.31	0.01	95.19	0.00	94.59	0.00	95.48	0.01			95.44	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1545364768
96.31	0.01	95.19	0.00	94.59	0.00	95.48	0.00			95.44	0.01	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4039651993
96.31	0.01	95.19	0.00	94.59	0.00	95.48	0.00			95.45	0.01	97.59	0.00	99.58	0.00	/workspace/coverage/default/4.chip_tap_straps_dev.1754828042
96.31	0.01	95.19	0.00	94.59	0.01	95.48	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.4109523497
96.31	0.01	95.19	0.00	94.60	0.01	95.48	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/14.chip_csr_rw.285741696
96.32	0.01	95.19	0.00	94.61	0.01	95.48	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/22.chip_tl_errors.906500546
96.32	0.01	95.19	0.00	94.61	0.01	95.48	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.221264843
96.32	0.01	95.19	0.00	94.62	0.01	95.48	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1607365615
96.32	0.01	95.19	0.00	94.63	0.01	95.48	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1573238283
96.32	0.01	95.19	0.00	94.64	0.01	95.48	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1735778846
96.32	0.01	95.19	0.00	94.64	0.00	95.48	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3111683894
96.32	0.01	95.19	0.00	94.64	0.00	95.49	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1596909525
96.32	0.01	95.19	0.00	94.64	0.00	95.49	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3728643814
96.32	0.01	95.19	0.00	94.64	0.00	95.50	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2250097511
96.33	0.01	95.19	0.00	94.64	0.00	95.50	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3721733315
96.33	0.01	95.19	0.00	94.64	0.00	95.51	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2317781924
96.33	0.01	95.19	0.00	94.64	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.xbar_error_random.4014647669
96.33	0.01	95.19	0.00	94.64	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1855014889
96.33	0.01	95.19	0.00	94.65	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.842588683
96.33	0.01	95.19	0.00	94.65	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.404319698
96.33	0.01	95.19	0.00	94.65	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.1155357370
96.33	0.01	95.19	0.00	94.66	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2644772425
96.33	0.01	95.19	0.00	94.66	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3814504882
96.33	0.01	95.19	0.00	94.67	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.94549338
96.33	0.01	95.19	0.00	94.67	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1555641732
96.33	0.01	95.19	0.00	94.67	0.01	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.203029073
96.33	0.01	95.19	0.01	94.67	0.00	95.51	0.00			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.4186011647
96.33	0.01	95.19	0.00	94.67	0.00	95.51	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.724268213
96.33	0.01	95.19	0.00	94.67	0.00	95.51	0.01			95.45	0.00	97.59	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.932715286

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3121714571
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2400904824
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1858196848
/workspace/coverage/cover_reg_top/0.chip_csr_rw.602535947
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1717622662
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1949179613
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1531072117
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2128353890
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3569560493
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1850752531
/workspace/coverage/cover_reg_top/0.xbar_random.3743773195
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3627696976
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.50218579
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1806374060
/workspace/coverage/cover_reg_top/0.xbar_same_source.1603556423
/workspace/coverage/cover_reg_top/0.xbar_smoke.4251077495
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3084713038
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.485208924
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3430386448
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1184369289
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1147037349
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2222313598
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2159166124
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3147537699
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1562274880
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1040512041
/workspace/coverage/cover_reg_top/1.chip_csr_rw.814566002
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1123676904
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4154758061
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3722238459
/workspace/coverage/cover_reg_top/1.chip_tl_errors.4257135119
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.781640146
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.458294103
/workspace/coverage/cover_reg_top/1.xbar_error_random.4210477902
/workspace/coverage/cover_reg_top/1.xbar_random.1521939349
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3662380845
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1530484058
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1068247937
/workspace/coverage/cover_reg_top/1.xbar_same_source.3231173628
/workspace/coverage/cover_reg_top/1.xbar_smoke.1945876820
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2638070035
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.4220100933
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4140623482
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1423061741
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.634981839
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.752018060
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1701090915
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1208596760
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.473233577
/workspace/coverage/cover_reg_top/10.chip_csr_rw.172521936
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3738633881
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1007946746
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1988163521
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.125809825
/workspace/coverage/cover_reg_top/10.xbar_error_random.2091991229
/workspace/coverage/cover_reg_top/10.xbar_random.545820719
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2129756676
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.388526849
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.929861565
/workspace/coverage/cover_reg_top/10.xbar_same_source.3573631766
/workspace/coverage/cover_reg_top/10.xbar_smoke.3887602365
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3967381742
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3881546143
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1228064927
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2618091970
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1534937717
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2106319924
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.826451331
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4212355313
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2136189288
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2746989253
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2728145344
/workspace/coverage/cover_reg_top/11.chip_tl_errors.23826490
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.179760236
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.9322737
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.818520767
/workspace/coverage/cover_reg_top/11.xbar_error_random.2346699999
/workspace/coverage/cover_reg_top/11.xbar_random.130607046
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2226631484
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2045412429
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3616139516
/workspace/coverage/cover_reg_top/11.xbar_same_source.861459713
/workspace/coverage/cover_reg_top/11.xbar_smoke.1818905410
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3054930776
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3627923762
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2989763746
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2999194242
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1115117517
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3792962455
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.132180977
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.4159648525
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3106950202
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1290744395
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.386961815
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.642786844
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2309648722
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2493173007
/workspace/coverage/cover_reg_top/12.xbar_error_random.4190360528
/workspace/coverage/cover_reg_top/12.xbar_random.1484488628
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.999966423
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3521660370
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3354654513
/workspace/coverage/cover_reg_top/12.xbar_same_source.1903084973
/workspace/coverage/cover_reg_top/12.xbar_smoke.466829536
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1031218384
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.703656254
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1358132505
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1087500490
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3811322671
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1203539653
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.372821120
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.70880406
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1422005744
/workspace/coverage/cover_reg_top/13.chip_csr_rw.411446980
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.633392506
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1883577516
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2431007598
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.740539345
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3106466469
/workspace/coverage/cover_reg_top/13.xbar_error_random.3972904249
/workspace/coverage/cover_reg_top/13.xbar_random.903284139
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3342182946
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2656653479
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.278955611
/workspace/coverage/cover_reg_top/13.xbar_same_source.1738202989
/workspace/coverage/cover_reg_top/13.xbar_smoke.1326536151
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3801263762
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3245733789
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2513411443
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2496949667
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4264713854
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.4011975409
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.283339530
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2718855716
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2590611419
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1353247785
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2141039676
/workspace/coverage/cover_reg_top/14.xbar_error_random.2571011295
/workspace/coverage/cover_reg_top/14.xbar_random.399022923
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.4108098967
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2142390474
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2910838874
/workspace/coverage/cover_reg_top/14.xbar_same_source.2772637913
/workspace/coverage/cover_reg_top/14.xbar_smoke.2830685490
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2508583834
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1672142924
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1844560433
/workspace/coverage/cover_reg_top/14.xbar_stress_all.2595369186
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2240804084
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3175534109
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1264388593
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2695096264
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2110089209
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/workspace/coverage/default/21.chip_sw_all_escalation_resets.2981016373
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2568974209
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1338417562
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329798089
/workspace/coverage/default/26.chip_sw_all_escalation_resets.2214881172
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760606486
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.732511357
/workspace/coverage/default/29.chip_sw_all_escalation_resets.132083591
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2172342004
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1979182095
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.330973905
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3264758063
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3453524449
/workspace/coverage/default/3.chip_sw_uart_tx_rx.115433250
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2712183254
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1305575718
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.85041655
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3847478353
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2767463345
/workspace/coverage/default/3.chip_tap_straps_dev.1066930268
/workspace/coverage/default/3.chip_tap_straps_prod.3904560744
/workspace/coverage/default/3.chip_tap_straps_rma.3699525314
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3413028945
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3778679431
/workspace/coverage/default/31.chip_sw_all_escalation_resets.4237049087
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.731773634
/workspace/coverage/default/33.chip_sw_all_escalation_resets.928209991
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3131496590
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3586529071
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1103010398
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2793336692
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3894694264
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736362622
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100288418
/workspace/coverage/default/39.chip_sw_all_escalation_resets.728887497
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3684715176
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1377647700
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2215289940
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3819698573
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2799915773
/workspace/coverage/default/4.chip_sw_uart_tx_rx.4197019677
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3746591001
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3537954762
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.428566783
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3809270958
/workspace/coverage/default/4.chip_tap_straps_prod.3171752066
/workspace/coverage/default/4.chip_tap_straps_rma.3091373134
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1717030396
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441596051
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2541060214
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1475066981
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1576566800
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2762721249
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.727450738
/workspace/coverage/default/44.chip_sw_all_escalation_resets.988071335
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383884428
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2703914838
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2271280187
/workspace/coverage/default/47.chip_sw_all_escalation_resets.425860604
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090808356
/workspace/coverage/default/48.chip_sw_all_escalation_resets.279903149
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1142976852
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1260008006
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1686025757
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3672612524
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3265523587
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3656344376
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2378256975
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1780306387
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2546077736
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2033479093
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2927609170
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1119314749
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.847452163
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3711889361
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491954617
/workspace/coverage/default/55.chip_sw_all_escalation_resets.279820876
/workspace/coverage/default/57.chip_sw_all_escalation_resets.829668066
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3765433307
/workspace/coverage/default/58.chip_sw_all_escalation_resets.4177668948
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3877768515
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3693066482
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3652952363
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2336295612
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3463468954
/workspace/coverage/default/60.chip_sw_all_escalation_resets.454668378
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1595659855
/workspace/coverage/default/61.chip_sw_all_escalation_resets.936064744
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4126926736
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1191563600
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3637751116
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3711372920
/workspace/coverage/default/64.chip_sw_all_escalation_resets.4289277848
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1318408479
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4075033843
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.616371486
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1394036093
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099316004
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2839282573
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3618376207
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2512335937
/workspace/coverage/default/7.chip_sw_all_escalation_resets.956704929
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3728543918
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3171958486
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1381823580
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1379455401
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388555489
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2410134717
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2558065777
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.808112719
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1374284166
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186737350
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2840460229
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040011744
/workspace/coverage/default/76.chip_sw_all_escalation_resets.4251935586
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1019182060
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1537423283
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3654053025
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2252337618
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3695500297
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3758866729
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.105318658
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2074115685
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3576680756
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392038715
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2896097555
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.276425287
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2405169407
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770458869
/workspace/coverage/default/85.chip_sw_all_escalation_resets.549959668
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2571077177
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593688425
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3065516573
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4011187879
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.671475112
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2568227654
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830313921
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3350132906
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3618705780
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1932662484
/workspace/coverage/default/93.chip_sw_all_escalation_resets.4275414199
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1066749222
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1813568317
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1791772866
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1205232987
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2838421806
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2126100285
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4096008706
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.959948256
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3418033677
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3808646807
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2899906900
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3603307522
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4179104179
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2876388802
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.337816519

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Total test records in report: 2875

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T35	/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1390823279			Feb 07 04:12:50 PM PST 24	Feb 07 04:15:48 PM PST 24	587705974 ps
T36	/workspace/coverage/cover_reg_top/45.xbar_random_large_delays.3358272180			Feb 07 04:16:59 PM PST 24	Feb 07 04:22:37 PM PST 24	32009957087 ps
T37	/workspace/coverage/cover_reg_top/85.xbar_random.2632823855			Feb 07 04:22:48 PM PST 24	Feb 07 04:23:38 PM PST 24	563061740 ps
T50	/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.596636245			Feb 07 04:12:24 PM PST 24	Feb 07 04:25:42 PM PST 24	71668981036 ps
T257	/workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1522867385			Feb 07 04:13:37 PM PST 24	Feb 07 04:13:44 PM PST 24	40667825 ps
T105	/workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2299785706			Feb 07 04:22:04 PM PST 24	Feb 07 04:23:48 PM PST 24	9426478761 ps
T259	/workspace/coverage/cover_reg_top/42.xbar_stress_all.186448094			Feb 07 04:16:40 PM PST 24	Feb 07 04:20:29 PM PST 24	2467846687 ps
T258	/workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3403332071			Feb 07 04:13:41 PM PST 24	Feb 07 04:31:15 PM PST 24	57602544833 ps
T312	/workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2328474447			Feb 07 04:24:06 PM PST 24	Feb 07 04:25:32 PM PST 24	7719831790 ps
T169	/workspace/coverage/cover_reg_top/96.xbar_stress_all.3210624612			Feb 07 04:24:43 PM PST 24	Feb 07 04:25:05 PM PST 24	289475937 ps
T170	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2385416453			Feb 07 04:14:24 PM PST 24	Feb 07 04:16:25 PM PST 24	1533379147 ps
T116	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1747992301			Feb 07 04:16:07 PM PST 24	Feb 07 04:16:36 PM PST 24	763655309 ps
T372	/workspace/coverage/cover_reg_top/22.xbar_random.183878706			Feb 07 04:13:39 PM PST 24	Feb 07 04:15:06 PM PST 24	2023292214 ps
T417	/workspace/coverage/cover_reg_top/89.xbar_same_source.355026315			Feb 07 04:23:35 PM PST 24	Feb 07 04:24:10 PM PST 24	1156989156 ps
T423	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3569560493			Feb 07 04:11:27 PM PST 24	Feb 07 04:23:00 PM PST 24	40019667231 ps
T405	/workspace/coverage/cover_reg_top/6.xbar_error_random.1050815498			Feb 07 04:11:51 PM PST 24	Feb 07 04:13:26 PM PST 24	2769509056 ps
T422	/workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.863473566			Feb 07 04:23:19 PM PST 24	Feb 07 04:27:46 PM PST 24	14884299432 ps
T114	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3830652745			Feb 07 04:12:37 PM PST 24	Feb 07 04:19:02 PM PST 24	11788091798 ps
T424	/workspace/coverage/cover_reg_top/65.xbar_access_same_device.2337067051			Feb 07 04:19:52 PM PST 24	Feb 07 04:21:30 PM PST 24	2377213347 ps
T411	/workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3868186786			Feb 07 04:18:55 PM PST 24	Feb 07 04:23:12 PM PST 24	22285228999 ps
T429	/workspace/coverage/cover_reg_top/56.xbar_stress_all.2911131475			Feb 07 04:18:38 PM PST 24	Feb 07 04:18:53 PM PST 24	296179314 ps
T387	/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.4197743158			Feb 07 04:19:07 PM PST 24	Feb 07 04:49:09 PM PST 24	100200329647 ps
T415	/workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.2707804832			Feb 07 04:19:05 PM PST 24	Feb 07 04:19:12 PM PST 24	55812727 ps
T430	/workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.40513466			Feb 07 04:23:50 PM PST 24	Feb 07 04:25:35 PM PST 24	9335031683 ps
T376	/workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2275897503			Feb 07 04:19:15 PM PST 24	Feb 07 04:20:52 PM PST 24	8889328955 ps
T419	/workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1899859787			Feb 07 04:21:03 PM PST 24	Feb 07 04:21:49 PM PST 24	515147717 ps
T431	/workspace/coverage/cover_reg_top/91.xbar_access_same_device.3883567110			Feb 07 04:23:48 PM PST 24	Feb 07 04:25:15 PM PST 24	2313424966 ps
T425	/workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2817882086			Feb 07 04:14:17 PM PST 24	Feb 07 04:14:47 PM PST 24	243916082 ps
T406	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2779768058			Feb 07 04:16:27 PM PST 24	Feb 07 04:16:59 PM PST 24	81053958 ps
T33	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3456443508			Feb 07 04:12:03 PM PST 24	Feb 07 05:21:48 PM PST 24	28701524385 ps
T359	/workspace/coverage/cover_reg_top/49.xbar_access_same_device.2409779695			Feb 07 04:17:40 PM PST 24	Feb 07 04:18:54 PM PST 24	1444565333 ps
T605	/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2513411443			Feb 07 04:12:21 PM PST 24	Feb 07 04:12:27 PM PST 24	42258055 ps
T426	/workspace/coverage/cover_reg_top/66.xbar_smoke.3312371283			Feb 07 04:20:00 PM PST 24	Feb 07 04:20:12 PM PST 24	219569922 ps
T384	/workspace/coverage/cover_reg_top/69.xbar_access_same_device.807147566			Feb 07 04:20:19 PM PST 24	Feb 07 04:21:56 PM PST 24	2454075552 ps
T435	/workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2555026908			Feb 07 04:23:38 PM PST 24	Feb 07 04:23:44 PM PST 24	47091121 ps
T473	/workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2798982203			Feb 07 04:20:07 PM PST 24	Feb 07 04:20:14 PM PST 24	52876642 ps
T389	/workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.412538922			Feb 07 04:24:31 PM PST 24	Feb 07 04:25:08 PM PST 24	434739279 ps
T427	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2228248452			Feb 07 04:20:36 PM PST 24	Feb 07 04:22:05 PM PST 24	278461891 ps
T428	/workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3297920056			Feb 07 04:12:09 PM PST 24	Feb 07 04:13:29 PM PST 24	4605872193 ps
T115	/workspace/coverage/cover_reg_top/5.xbar_stress_all.1245162775			Feb 07 04:11:51 PM PST 24	Feb 07 04:16:35 PM PST 24	3374106257 ps
T562	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.610478613			Feb 07 04:18:13 PM PST 24	Feb 07 04:23:00 PM PST 24	670662413 ps
T418	/workspace/coverage/cover_reg_top/82.xbar_stress_all.1217248141			Feb 07 04:22:24 PM PST 24	Feb 07 04:23:10 PM PST 24	1439231225 ps
T390	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2461677065			Feb 07 04:11:40 PM PST 24	Feb 07 04:21:25 PM PST 24	4619778951 ps
T823	/workspace/coverage/cover_reg_top/77.xbar_access_same_device.1402831400			Feb 07 04:21:36 PM PST 24	Feb 07 04:21:46 PM PST 24	104766061 ps
T391	/workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.4279424155			Feb 07 04:15:05 PM PST 24	Feb 07 04:29:43 PM PST 24	46430385434 ps
T806	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1788805541			Feb 07 04:22:33 PM PST 24	Feb 07 04:25:41 PM PST 24	11079936367 ps
T817	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3419038064			Feb 07 04:22:02 PM PST 24	Feb 07 04:34:00 PM PST 24	38467682597 ps
T857	/workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.3929799158			Feb 07 04:16:57 PM PST 24	Feb 07 04:17:33 PM PST 24	314208490 ps
T407	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2877358357			Feb 07 04:11:46 PM PST 24	Feb 07 04:19:34 PM PST 24	2615181773 ps
T858	/workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1297922153			Feb 07 04:11:39 PM PST 24	Feb 07 04:13:11 PM PST 24	9000361938 ps
T412	/workspace/coverage/cover_reg_top/10.xbar_same_source.3573631766			Feb 07 04:12:06 PM PST 24	Feb 07 04:12:41 PM PST 24	508329358 ps
T433	/workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2456142826			Feb 07 04:20:19 PM PST 24	Feb 07 04:20:56 PM PST 24	993036031 ps
T410	/workspace/coverage/cover_reg_top/15.xbar_same_source.2681475459			Feb 07 04:12:31 PM PST 24	Feb 07 04:13:13 PM PST 24	546128319 ps
T409	/workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2479631300			Feb 07 04:20:15 PM PST 24	Feb 07 04:21:44 PM PST 24	5625750578 ps
T859	/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.458294103			Feb 07 04:11:41 PM PST 24	Feb 07 04:12:02 PM PST 24	199393508 ps
T434	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3050983345			Feb 07 04:20:52 PM PST 24	Feb 07 04:50:24 PM PST 24	90887281258 ps
T546	/workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2328956259			Feb 07 04:22:05 PM PST 24	Feb 07 04:22:12 PM PST 24	52392027 ps
T34	/workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1503279616			Feb 07 04:12:04 PM PST 24	Feb 07 04:18:24 PM PST 24	7454962450 ps
T413	/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3752520546			Feb 07 04:12:46 PM PST 24	Feb 07 04:13:42 PM PST 24	3254584084 ps
T420	/workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1581275559			Feb 07 04:13:32 PM PST 24	Feb 07 04:13:59 PM PST 24	221659726 ps
T416	/workspace/coverage/cover_reg_top/60.xbar_same_source.1843873863			Feb 07 04:19:13 PM PST 24	Feb 07 04:19:56 PM PST 24	487389365 ps
T388	/workspace/coverage/cover_reg_top/52.xbar_stress_all.729103993			Feb 07 04:18:07 PM PST 24	Feb 07 04:29:33 PM PST 24	16912401271 ps
T432	/workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2827304033			Feb 07 04:11:47 PM PST 24	Feb 07 04:13:24 PM PST 24	9831042140 ps
T414	/workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2843241516			Feb 07 04:15:26 PM PST 24	Feb 07 04:16:15 PM PST 24	543151501 ps
T386	/workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.489337064			Feb 07 04:12:02 PM PST 24	Feb 07 04:22:49 PM PST 24	34099397820 ps
T1	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.959948256			Feb 07 04:11:24 PM PST 24	Feb 07 04:15:30 PM PST 24	3991790988 ps
T2	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2760087121			Feb 07 04:11:23 PM PST 24	Feb 07 04:16:45 PM PST 24	5534617264 ps
T3	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2876388802			Feb 07 04:11:18 PM PST 24	Feb 07 04:15:15 PM PST 24	5416672083 ps
T7	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4179104179			Feb 07 04:11:26 PM PST 24	Feb 07 04:15:21 PM PST 24	5159852465 ps
T55	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4096008706			Feb 07 04:11:20 PM PST 24	Feb 07 04:16:41 PM PST 24	4635417602 ps
T56	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3808646807			Feb 07 04:11:23 PM PST 24	Feb 07 04:15:34 PM PST 24	4554700853 ps
T57	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3603307522			Feb 07 04:11:22 PM PST 24	Feb 07 04:16:59 PM PST 24	4681789562 ps
T58	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.337816519			Feb 07 04:11:31 PM PST 24	Feb 07 04:15:23 PM PST 24	4171364794 ps
T59	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2899906900			Feb 07 04:11:25 PM PST 24	Feb 07 04:15:12 PM PST 24	4420486298 ps
T60	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3418033677			Feb 07 04:11:21 PM PST 24	Feb 07 04:15:33 PM PST 24	4254387536 ps
T23	/workspace/coverage/default/4.chip_tap_straps_testunlock0.2951785623			Feb 07 04:56:59 PM PST 24	Feb 07 05:04:29 PM PST 24	8700234526 ps
T24	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1173002853			Feb 07 04:57:12 PM PST 24	Feb 07 05:02:26 PM PST 24	2652093668 ps
T25	/workspace/coverage/default/2.chip_sw_uart_tx_rx.4024021342			Feb 07 04:47:35 PM PST 24	Feb 07 05:06:13 PM PST 24	5950108468 ps
T85	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.539121416			Feb 07 04:50:11 PM PST 24	Feb 07 05:15:34 PM PST 24	6545633464 ps
T26	/workspace/coverage/default/83.chip_sw_all_escalation_resets.1083344786			Feb 07 05:04:07 PM PST 24	Feb 07 05:12:45 PM PST 24	4775442752 ps
T41	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2289401076			Feb 07 05:03:57 PM PST 24	Feb 07 05:13:53 PM PST 24	5468908880 ps
T47	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.944565295			Feb 07 04:32:06 PM PST 24	Feb 07 06:16:28 PM PST 24	31331492648 ps
T158	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3705671907			Feb 07 04:38:33 PM PST 24	Feb 07 04:49:39 PM PST 24	4350731240 ps
T91	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3219477394			Feb 07 04:52:46 PM PST 24	Feb 07 04:55:58 PM PST 24	2518850232 ps
T181	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1824283371			Feb 07 04:56:10 PM PST 24	Feb 07 05:14:40 PM PST 24	5642609224 ps
T171	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.56598231			Feb 07 04:35:19 PM PST 24	Feb 07 04:41:28 PM PST 24	3558721004 ps
T42	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3700543509			Feb 07 05:02:50 PM PST 24	Feb 07 05:10:32 PM PST 24	4965395608 ps
T208	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.85041655			Feb 07 04:56:53 PM PST 24	Feb 07 05:10:57 PM PST 24	6153265380 ps
T38	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.462096618			Feb 07 04:38:13 PM PST 24	Feb 07 07:37:15 PM PST 24	59430157036 ps
T159	/workspace/coverage/default/0.rom_e2e_smoke.1507088189			Feb 07 04:36:07 PM PST 24	Feb 07 05:16:44 PM PST 24	8885539008 ps
T214	/workspace/coverage/default/3.chip_sw_uart_tx_rx.115433250			Feb 07 04:55:46 PM PST 24	Feb 07 05:12:42 PM PST 24	5818830912 ps
T172	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.616371486			Feb 07 05:05:36 PM PST 24	Feb 07 05:14:33 PM PST 24	3696119792 ps
T160	/workspace/coverage/default/1.rom_e2e_static_critical.2896609191			Feb 07 04:51:11 PM PST 24	Feb 07 05:24:49 PM PST 24	11292247496 ps
T106	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3626859375			Feb 07 04:51:07 PM PST 24	Feb 07 05:01:39 PM PST 24	8081333658 ps
T224	/workspace/coverage/default/1.chip_sw_pattgen_ios.1433395437			Feb 07 04:37:26 PM PST 24	Feb 07 04:40:01 PM PST 24	2101804864 ps
T145	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1028227044			Feb 07 04:40:52 PM PST 24	Feb 07 05:31:30 PM PST 24	12069799316 ps
T357	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.821774865			Feb 07 04:40:33 PM PST 24	Feb 07 05:15:41 PM PST 24	9152383448 ps
T666	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.675401684			Feb 07 04:35:09 PM PST 24	Feb 07 04:43:03 PM PST 24	3177862890 ps
T146	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.815834211			Feb 07 04:37:17 PM PST 24	Feb 07 04:43:21 PM PST 24	4169430216 ps
T30	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.692211080			Feb 07 04:32:36 PM PST 24	Feb 07 04:37:23 PM PST 24	6052403810 ps
T157	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1613695144			Feb 07 04:58:07 PM PST 24	Feb 07 05:09:54 PM PST 24	4465130368 ps
T155	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3173800964			Feb 07 04:57:50 PM PST 24	Feb 07 05:07:50 PM PST 24	4851597392 ps
T156	/workspace/coverage/default/71.chip_sw_all_escalation_resets.1839297239			Feb 07 05:05:14 PM PST 24	Feb 07 05:19:08 PM PST 24	5780041212 ps
T358	/workspace/coverage/default/0.rom_e2e_asm_init_dev.1719287040			Feb 07 04:41:13 PM PST 24	Feb 07 05:15:04 PM PST 24	9297030567 ps
T107	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2126419580			Feb 07 04:45:31 PM PST 24	Feb 07 04:51:35 PM PST 24	4859198270 ps
T144	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2827211311			Feb 07 04:41:58 PM PST 24	Feb 07 05:10:41 PM PST 24	6402350630 ps
T51	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3920142936			Feb 07 04:33:27 PM PST 24	Feb 07 04:38:13 PM PST 24	3368579306 ps
T108	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.675826449			Feb 07 04:33:36 PM PST 24	Feb 07 05:32:22 PM PST 24	35414375546 ps
T39	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1051758898			Feb 07 04:44:15 PM PST 24	Feb 07 04:51:29 PM PST 24	3299714002 ps
T219	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1383985580			Feb 07 04:39:02 PM PST 24	Feb 07 04:53:31 PM PST 24	4517040860 ps
T84	/workspace/coverage/default/2.chip_sw_power_sleep_load.3994670793			Feb 07 04:53:18 PM PST 24	Feb 07 05:04:47 PM PST 24	10575371832 ps
T202	/workspace/coverage/default/2.chip_plic_all_irqs_0.981368724			Feb 07 04:53:56 PM PST 24	Feb 07 05:15:49 PM PST 24	6057875890 ps
T228	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2405169407			Feb 07 05:03:20 PM PST 24	Feb 07 05:12:04 PM PST 24	4838276168 ps
T211	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3665875335			Feb 07 04:48:57 PM PST 24	Feb 07 05:07:20 PM PST 24	5445479540 ps
T226	/workspace/coverage/default/98.chip_sw_all_escalation_resets.2838421806			Feb 07 05:04:18 PM PST 24	Feb 07 05:14:40 PM PST 24	5346333226 ps
T667	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2921950751			Feb 07 05:02:02 PM PST 24	Feb 07 05:12:48 PM PST 24	5154342898 ps
T40	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4010163059			Feb 07 04:31:45 PM PST 24	Feb 07 05:55:57 PM PST 24	44582641475 ps
T150	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2311391988			Feb 07 04:50:57 PM PST 24	Feb 07 05:00:53 PM PST 24	5216400144 ps
T860	/workspace/coverage/default/0.chip_sw_aes_enc.1089615831			Feb 07 04:34:03 PM PST 24	Feb 07 04:38:29 PM PST 24	3037361000 ps
T112	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4280682978			Feb 07 04:39:10 PM PST 24	Feb 07 04:45:57 PM PST 24	3523268528 ps
T243	/workspace/coverage/default/64.chip_sw_all_escalation_resets.4289277848			Feb 07 05:04:28 PM PST 24	Feb 07 05:12:10 PM PST 24	5080660112 ps
T184	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3355726577			Feb 07 04:59:13 PM PST 24	Feb 07 05:05:37 PM PST 24	3540630140 ps
T861	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1734651892			Feb 07 04:54:18 PM PST 24	Feb 07 04:58:56 PM PST 24	3059245460 ps
T97	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1325029206			Feb 07 05:01:59 PM PST 24	Feb 07 05:08:33 PM PST 24	6106115165 ps
T98	/workspace/coverage/default/0.rom_raw_unlock.226110904			Feb 07 04:37:16 PM PST 24	Feb 07 05:10:45 PM PST 24	14616724599 ps
T662	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2773581785			Feb 07 04:34:37 PM PST 24	Feb 07 04:47:36 PM PST 24	9681818016 ps
T862	/workspace/coverage/default/0.chip_sw_aes_entropy.1283499021			Feb 07 04:36:15 PM PST 24	Feb 07 04:39:35 PM PST 24	2668190520 ps
T92	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1573238283			Feb 07 04:35:57 PM PST 24	Feb 07 04:54:49 PM PST 24	5570503024 ps
T43	/workspace/coverage/default/2.chip_tap_straps_rma.2136366454			Feb 07 04:53:37 PM PST 24	Feb 07 04:58:53 PM PST 24	4363979363 ps
T182	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1103010398			Feb 07 05:00:57 PM PST 24	Feb 07 05:09:08 PM PST 24	4407335136 ps
T229	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3061256887			Feb 07 04:59:57 PM PST 24	Feb 07 05:13:08 PM PST 24	6244557520 ps
T45	/workspace/coverage/default/2.chip_tap_straps_testunlock0.2039622901			Feb 07 04:52:40 PM PST 24	Feb 07 04:58:10 PM PST 24	6973174668 ps
T93	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2442783655			Feb 07 04:53:46 PM PST 24	Feb 07 04:58:44 PM PST 24	2970026941 ps
T8	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.222208046			Feb 07 04:46:00 PM PST 24	Feb 07 05:09:52 PM PST 24	21810353580 ps
T76	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830313921			Feb 07 05:01:51 PM PST 24	Feb 07 05:08:11 PM PST 24	3823736556 ps
T9	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.418160267			Feb 07 04:35:30 PM PST 24	Feb 07 04:59:08 PM PST 24	22606284808 ps
T77	/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.3710129294			Feb 07 04:40:02 PM PST 24	Feb 07 05:16:44 PM PST 24	8906557570 ps
T78	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2521297063			Feb 07 04:34:46 PM PST 24	Feb 07 04:42:44 PM PST 24	4080579294 ps
T79	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.385362464			Feb 07 04:39:55 PM PST 24	Feb 07 04:58:06 PM PST 24	5507825100 ps
T80	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1989742465			Feb 07 04:53:08 PM PST 24	Feb 07 05:01:31 PM PST 24	3755111052 ps
T81	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3169446892			Feb 07 04:32:42 PM PST 24	Feb 07 04:43:43 PM PST 24	4513281704 ps
T82	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4148521191			Feb 07 04:34:04 PM PST 24	Feb 07 04:45:08 PM PST 24	6570650268 ps
T83	/workspace/coverage/default/0.chip_tap_straps_prod.3768037986			Feb 07 04:36:01 PM PST 24	Feb 07 04:49:49 PM PST 24	7042602601 ps
T100	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1305575718			Feb 07 04:57:15 PM PST 24	Feb 07 05:22:05 PM PST 24	13100302453 ps
T863	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2226149190			Feb 07 04:52:24 PM PST 24	Feb 07 05:04:46 PM PST 24	4643330552 ps
T864	/workspace/coverage/default/2.rom_e2e_static_critical.2171274550			Feb 07 05:01:07 PM PST 24	Feb 07 05:41:36 PM PST 24	11239263280 ps
T752	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2033479093			Feb 07 05:01:23 PM PST 24	Feb 07 05:06:55 PM PST 24	3314374544 ps
T183	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1393535895			Feb 07 04:51:07 PM PST 24	Feb 07 04:59:55 PM PST 24	4980230984 ps
T130	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2634749944			Feb 07 04:37:24 PM PST 24	Feb 07 04:43:16 PM PST 24	3035238498 ps
T99	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4096415303			Feb 07 04:39:16 PM PST 24	Feb 07 05:19:36 PM PST 24	31459910375 ps
T199	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.671475112			Feb 07 05:04:21 PM PST 24	Feb 07 05:10:46 PM PST 24	3914425890 ps
T865	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3478756113			Feb 07 04:36:48 PM PST 24	Feb 07 04:43:46 PM PST 24	3219471994 ps
T866	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1491064804			Feb 07 05:00:28 PM PST 24	Feb 07 05:18:05 PM PST 24	5765974492 ps
T10	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1381270557			Feb 07 04:53:33 PM PST 24	Feb 07 04:59:52 PM PST 24	6673279076 ps
T689	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1335931730			Feb 07 04:50:00 PM PST 24	Feb 07 05:24:25 PM PST 24	22452919730 ps
T867	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.915734167			Feb 07 04:42:04 PM PST 24	Feb 07 04:51:10 PM PST 24	5694958534 ps
T124	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.311657643			Feb 07 04:32:07 PM PST 24	Feb 07 04:40:54 PM PST 24	4479689092 ps
T236	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2075023864			Feb 07 04:33:41 PM PST 24	Feb 07 05:00:57 PM PST 24	18750483317 ps
T868	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4236909071			Feb 07 04:49:58 PM PST 24	Feb 07 04:55:03 PM PST 24	3208285300 ps
T4	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4251165855			Feb 07 04:53:00 PM PST 24	Feb 07 04:57:59 PM PST 24	3131219233 ps
T314	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1338417562			Feb 07 04:58:54 PM PST 24	Feb 07 05:04:46 PM PST 24	3898036940 ps
T318	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2411277007			Feb 07 04:44:10 PM PST 24	Feb 07 04:51:12 PM PST 24	4312974400 ps
T319	/workspace/coverage/default/2.chip_sw_example_flash.2356992626			Feb 07 04:52:35 PM PST 24	Feb 07 04:55:44 PM PST 24	2458062240 ps
T161	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2645543268			Feb 07 04:34:26 PM PST 24	Feb 07 04:46:44 PM PST 24	6108317284 ps
T179	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3711889361			Feb 07 05:04:51 PM PST 24	Feb 07 05:14:27 PM PST 24	4929802826 ps
T94	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3316931013			Feb 07 04:51:07 PM PST 24	Feb 07 05:02:09 PM PST 24	4349245928 ps
T320	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2761542358			Feb 07 04:32:09 PM PST 24	Feb 07 04:49:40 PM PST 24	5937283684 ps
T113	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2499817418			Feb 07 04:50:52 PM PST 24	Feb 07 04:55:14 PM PST 24	3296020936 ps
T321	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3934534253			Feb 07 04:40:02 PM PST 24	Feb 07 04:44:16 PM PST 24	3086759728 ps
T322	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2303363442			Feb 07 04:59:37 PM PST 24	Feb 07 05:05:51 PM PST 24	3149548890 ps
T223	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4093524106			Feb 07 04:33:01 PM PST 24	Feb 07 04:49:34 PM PST 24	5012158076 ps
T696	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1088947905			Feb 07 04:41:59 PM PST 24	Feb 07 05:21:53 PM PST 24	9036683552 ps
T205	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1267852674			Feb 07 04:47:35 PM PST 24	Feb 07 05:04:30 PM PST 24	6287051064 ps
T207	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2404556321			Feb 07 04:59:05 PM PST 24	Feb 07 05:14:12 PM PST 24	5171051008 ps
T206	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3596258225			Feb 07 04:53:45 PM PST 24	Feb 07 04:58:43 PM PST 24	2969051351 ps
T869	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2163823731			Feb 07 04:32:26 PM PST 24	Feb 07 04:38:58 PM PST 24	3154708900 ps
T870	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2017596408			Feb 07 04:37:14 PM PST 24	Feb 07 04:42:37 PM PST 24	2738763066 ps
T871	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1384805897			Feb 07 04:37:12 PM PST 24	Feb 07 04:42:07 PM PST 24	2439904600 ps
T151	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3728543918			Feb 07 04:57:20 PM PST 24	Feb 07 05:11:20 PM PST 24	11226143729 ps
T872	/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1790233104			Feb 07 04:50:27 PM PST 24	Feb 07 05:27:47 PM PST 24	9060666188 ps
T16	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.905315024			Feb 07 04:38:49 PM PST 24	Feb 07 04:42:49 PM PST 24	3539568248 ps
T360	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3778679431			Feb 07 05:02:02 PM PST 24	Feb 07 05:08:40 PM PST 24	3736992308 ps
T361	/workspace/coverage/default/1.chip_sw_example_concurrency.755496388			Feb 07 04:37:08 PM PST 24	Feb 07 04:41:04 PM PST 24	3014376594 ps
T362	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1935717852			Feb 07 04:47:43 PM PST 24	Feb 07 04:56:36 PM PST 24	5423619917 ps
T363	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.732511357			Feb 07 04:59:33 PM PST 24	Feb 07 05:06:05 PM PST 24	3943082068 ps
T364	/workspace/coverage/default/1.rom_keymgr_functest.2295649087			Feb 07 04:46:33 PM PST 24	Feb 07 04:57:56 PM PST 24	4221844150 ps
T152	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4237784547			Feb 07 04:49:32 PM PST 24	Feb 07 04:54:40 PM PST 24	3092186765 ps
T365	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1195381910			Feb 07 04:38:52 PM PST 24	Feb 07 04:55:27 PM PST 24	5450400484 ps
T52	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.808112719			Feb 07 05:04:00 PM PST 24	Feb 07 05:09:25 PM PST 24	3381889434 ps
T65	/workspace/coverage/default/0.chip_sw_hmac_enc.3196552423			Feb 07 04:35:39 PM PST 24	Feb 07 04:42:29 PM PST 24	3347272594 ps
T66	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736362622			Feb 07 05:02:22 PM PST 24	Feb 07 05:08:41 PM PST 24	3915191886 ps
T67	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1177952741			Feb 07 04:50:41 PM PST 24	Feb 07 05:44:13 PM PST 24	18758937111 ps
T68	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2317781924			Feb 07 04:41:31 PM PST 24	Feb 07 04:48:49 PM PST 24	3947752224 ps
T69	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1196800983			Feb 07 04:58:03 PM PST 24	Feb 07 05:13:40 PM PST 24	6084122592 ps
T70	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1417089536			Feb 07 05:00:02 PM PST 24	Feb 07 05:08:05 PM PST 24	3402219326 ps
T121	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.641098464			Feb 07 04:43:55 PM PST 24	Feb 07 04:47:56 PM PST 24	2352321839 ps
T262	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2220128562			Feb 07 04:48:31 PM PST 24	Feb 07 04:51:38 PM PST 24	2538678030 ps
T227	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2215289940			Feb 07 04:57:26 PM PST 24	Feb 07 05:09:09 PM PST 24	5128936280 ps
T280	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4209005379			Feb 07 04:48:32 PM PST 24	Feb 07 05:21:58 PM PST 24	20022754647 ps
T61	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677031320			Feb 07 05:02:02 PM PST 24	Feb 07 05:08:06 PM PST 24	3157247904 ps
T71	/workspace/coverage/default/0.chip_plic_all_irqs_0.4217667185			Feb 07 04:35:05 PM PST 24	Feb 07 04:59:59 PM PST 24	6086314680 ps
T72	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1025126285			Feb 07 04:37:10 PM PST 24	Feb 07 04:41:44 PM PST 24	2580553188 ps
T281	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1780306387			Feb 07 05:01:53 PM PST 24	Feb 07 05:09:17 PM PST 24	4176545960 ps
T282	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3904302574			Feb 07 04:44:21 PM PST 24	Feb 07 04:51:22 PM PST 24	5146144620 ps
T283	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090808356			Feb 07 05:03:15 PM PST 24	Feb 07 05:09:42 PM PST 24	3635063644 ps
T101	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3746591001			Feb 07 04:56:11 PM PST 24	Feb 07 05:46:23 PM PST 24	13717211041 ps
T284	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2943320769			Feb 07 04:41:40 PM PST 24	Feb 07 05:08:42 PM PST 24	6933920111 ps
T873	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2172342004			Feb 07 04:56:18 PM PST 24	Feb 07 05:06:25 PM PST 24	6318013176 ps
T874	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3643222177			Feb 07 04:43:09 PM PST 24	Feb 07 04:54:36 PM PST 24	6588295356 ps
T209	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1929249642			Feb 07 04:38:45 PM PST 24	Feb 07 04:57:50 PM PST 24	5147696052 ps
T875	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.299534609			Feb 07 04:56:42 PM PST 24	Feb 07 05:02:03 PM PST 24	2925106972 ps
T401	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857423701			Feb 07 05:02:35 PM PST 24	Feb 07 05:10:15 PM PST 24	3900460122 ps
T663	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2151938222			Feb 07 04:42:26 PM PST 24	Feb 07 05:20:44 PM PST 24	9002980684 ps
T133	/workspace/coverage/default/1.chip_plic_all_irqs_10.4035493611			Feb 07 04:43:49 PM PST 24	Feb 07 04:55:47 PM PST 24	3515074544 ps
T95	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1791660051			Feb 07 04:46:19 PM PST 24	Feb 07 04:58:57 PM PST 24	5412943785 ps
T62	/workspace/coverage/default/49.chip_sw_all_escalation_resets.1260008006			Feb 07 05:02:54 PM PST 24	Feb 07 05:11:47 PM PST 24	4552056236 ps
T876	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1587327975			Feb 07 04:38:22 PM PST 24	Feb 07 05:25:45 PM PST 24	23289198247 ps
T658	/workspace/coverage/default/4.chip_tap_straps_dev.1754828042			Feb 07 04:56:10 PM PST 24	Feb 07 05:16:04 PM PST 24	10686423503 ps
T877	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3171958486			Feb 07 04:58:03 PM PST 24	Feb 07 05:10:07 PM PST 24	4506210224 ps
T664	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3871380771			Feb 07 04:32:37 PM PST 24	Feb 07 04:47:46 PM PST 24	7731953590 ps
T878	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1545364768			Feb 07 04:43:06 PM PST 24	Feb 07 04:57:01 PM PST 24	8117920587 ps
T180	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2981016373			Feb 07 04:59:20 PM PST 24	Feb 07 05:10:34 PM PST 24	5050558708 ps
T654	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2813024841			Feb 07 05:00:33 PM PST 24	Feb 07 05:07:53 PM PST 24	3332147194 ps
T879	/workspace/coverage/default/1.chip_sw_aes_enc.2370366159			Feb 07 04:39:50 PM PST 24	Feb 07 04:43:06 PM PST 24	2401800520 ps
T880	/workspace/coverage/default/1.chip_tap_straps_dev.4030043959			Feb 07 04:45:00 PM PST 24	Feb 07 04:48:44 PM PST 24	3080509933 ps
T102	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.867919772			Feb 07 04:43:53 PM PST 24	Feb 07 04:58:06 PM PST 24	4993621068 ps
T881	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.837033151			Feb 07 04:49:02 PM PST 24	Feb 07 04:55:47 PM PST 24	6168079185 ps
T230	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2362771419			Feb 07 04:48:41 PM PST 24	Feb 07 05:05:30 PM PST 24	4690034778 ps
T149	/workspace/coverage/default/1.chip_sw_flash_init.1817903545			Feb 07 04:37:52 PM PST 24	Feb 07 05:18:24 PM PST 24	22509988940 ps
T215	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3809270958			Feb 07 04:56:21 PM PST 24	Feb 07 05:10:57 PM PST 24	5238590968 ps
T691	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2294769152			Feb 07 04:59:17 PM PST 24	Feb 07 05:12:41 PM PST 24	5596485068 ps
T665	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448545762			Feb 07 04:59:09 PM PST 24	Feb 07 05:07:18 PM PST 24	4145461416 ps
T882	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.258095567			Feb 07 04:38:54 PM PST 24	Feb 07 04:58:13 PM PST 24	9319523804 ps
T402	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3894694264			Feb 07 05:01:22 PM PST 24	Feb 07 05:12:40 PM PST 24	5262220930 ps
T883	/workspace/coverage/default/1.chip_sw_aes_smoketest.2062258208			Feb 07 04:47:22 PM PST 24	Feb 07 04:52:12 PM PST 24	2748089160 ps
T246	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.249615571			Feb 07 04:37:13 PM PST 24	Feb 07 04:41:34 PM PST 24	3184026072 ps
T722	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770458869			Feb 07 05:05:01 PM PST 24	Feb 07 05:11:12 PM PST 24	3895815342 ps
T715	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2133617463			Feb 07 05:00:50 PM PST 24	Feb 07 05:13:20 PM PST 24	5921095672 ps
T884	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3072331846			Feb 07 04:39:46 PM PST 24	Feb 07 04:46:11 PM PST 24	3388321723 ps
T885	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2674173058			Feb 07 04:50:19 PM PST 24	Feb 07 04:55:01 PM PST 24	2575467097 ps
T225	/workspace/coverage/default/2.chip_sw_pattgen_ios.3903319789			Feb 07 04:47:45 PM PST 24	Feb 07 04:50:46 PM PST 24	2188936920 ps
T886	/workspace/coverage/default/0.chip_sw_csrng_smoketest.4132184732			Feb 07 04:37:16 PM PST 24	Feb 07 04:39:56 PM PST 24	2997007268 ps
T244	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2406167305			Feb 07 04:41:36 PM PST 24	Feb 07 04:52:50 PM PST 24	5069348198 ps
T189	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1401555003			Feb 07 04:33:15 PM PST 24	Feb 07 05:11:38 PM PST 24	22378579970 ps
T31	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2840559886			Feb 07 04:36:56 PM PST 24	Feb 07 04:42:21 PM PST 24	5095038212 ps
T19	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1604651441			Feb 07 04:47:20 PM PST 24	Feb 07 04:52:43 PM PST 24	4428249196 ps
T366	/workspace/coverage/default/85.chip_sw_all_escalation_resets.549959668			Feb 07 05:03:39 PM PST 24	Feb 07 05:12:46 PM PST 24	4761870376 ps
T367	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3425327218			Feb 07 04:48:53 PM PST 24	Feb 07 04:53:42 PM PST 24	4195569640 ps
T368	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1104910183			Feb 07 04:59:21 PM PST 24	Feb 07 05:37:48 PM PST 24	12830129824 ps
T120	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3257069132			Feb 07 04:51:58 PM PST 24	Feb 07 05:00:53 PM PST 24	4805452088 ps