| | | | | | | |
tb.dut.top_earlgrey.scanmodeKnown
| 0 | 0 | 398938010 | 398938010 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AlertsKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.AonWkupReqKnownO_A
| 0 | 0 | 1338259 | 1162257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTckKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTmsKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftJtagTrstKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DftStrapsKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioKnownO_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.DioOeKnownO_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 99283020 | 5 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTckKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTmsKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.LcJtagTrstKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioKnownO_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.MioOeKnownO_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PinmuxWkupStable_A
| 0 | 0 | 1338259 | 4287 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.PwrMgrStrapSampleOnce0_A
| 0 | 0 | 99283020 | 1628 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTckKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTmsKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.RvJtagTrstKnown_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlAReadyKnownO_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.TlDValidKnownO_A
| 0 | 0 | 99283020 | 98611750 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWakeDetectActiveKnownO_A
| 0 | 0 | 1338259 | 1162257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.UsbWkupReqKnownO_A
| 0 | 0 | 1338259 | 1162257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.DftTapOff0_A
| 0 | 0 | 99283020 | 26014583 | 0 | 264 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnClear_A
| 0 | 0 | 99283020 | 2942824 | 0 | 6 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev0_A
| 0 | 0 | 99283020 | 1393 | 0 | 93 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSetRev1_A
| 0 | 0 | 99283020 | 1393 | 0 | 93 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.LcHwDebugEnSet_A
| 0 | 0 | 99283020 | 1393 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff0_A
| 0 | 0 | 99283020 | 253 | 0 | 186 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.RvTapOff1_A
| 0 | 0 | 99283020 | 22493946 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.TapStrapKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap0_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.dft_strap1_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap0_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tap_strap1_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tck_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdi_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tdo_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.tms_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.trst_idxRange_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.FunctionCheck_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a.gen_no_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b.gen_no_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en.gen_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98605209 | 0 | 2871 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en.gen_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98605209 | 0 | 2871 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en.gen_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98605209 | 0 | 2871 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en.gen_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98605209 | 0 | 2871 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.OutputsKnown_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en.gen_no_flops.OutputDelay_A
| 0 | 0 | 99283020 | 98611853 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 828 | 708 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_rst_por_aon_n_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 1671 | 716 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.en2addrHit
| 0 | 0 | 121002806 | 565196 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.reAfterRv
| 0 | 0 | 121002806 | 565196 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.rePulse
| 0 | 0 | 121002806 | 415001 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 190872 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 393 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 1567889 | 31 | 0 | 927 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 1567889 | 31 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 121002806 | 424 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 1567889 | 134 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 391 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 395 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 136587 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 130378 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 127658 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 318 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 318 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 318 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 318 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 318 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 119595 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 299 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 299 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 299 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 299 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 299 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 132531 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 328 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 328 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 328 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 328 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 328 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 137832 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 346 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 346 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 346 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 346 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 346 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 127907 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 320 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 320 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 320 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 320 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 320 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 146490 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 365 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 365 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 365 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 365 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 365 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 130953 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 326 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 327 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 140976 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 347 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 347 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 347 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 346 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 348 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 115819 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 289 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 289 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 289 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 289 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 289 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 121547 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 305 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 130413 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 324 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 135439 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 340 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 143930 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 131710 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 327 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 327 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 327 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 327 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 327 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 131992 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 329 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 329 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 329 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 329 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 329 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 129793 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 323 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 148258 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 367 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 367 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 367 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 367 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 368 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 119323 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 298 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 299 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 127242 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 317 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 317 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 317 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 317 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 317 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 140463 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 353 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 353 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 353 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 353 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 353 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 144898 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 356 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.BusySrcReqChk_A
| 0 | 0 | 121002806 | 129137 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.DstReqKnown_A
| 0 | 0 | 1567889 | 1359995 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.SrcBusyKnown_A
| 0 | 0 | 121002806 | 120203466 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 1567889 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 1567889 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 121002806 | 322 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.wePulse
| 0 | 0 | 121002806 | 150195 | 0 | 0 |
|
tb.dut.top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.WakeDetectActiveAonKnown_A
| 0 | 0 | 1338259 | 1162257 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable0_A
| 0 | 0 | 391480632 | 9 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable1_A
| 0 | 0 | 391480632 | 23581718 | 0 | 82 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable2_A
| 0 | 0 | 391480632 | 62970278 | 0 | 90 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3Rev_A
| 0 | 0 | 391480632 | 323714967 | 0 | 1914 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexFetchEnable3_A
| 0 | 0 | 391480632 | 323716775 | 0 | 1817 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexInstrIntgErrCheck_A
| 0 | 0 | 391480632 | 156 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmIbexLoadRespIntgErrCheck_A
| 0 | 0 | 391480632 | 588 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 391480632 | 2 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 391480632 | 33465779 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 391480632 | 27708677 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DataKnown_A
| 0 | 0 | 391480632 | 45902962 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.DepthKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.RvalidKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.WreadyKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DataKnown_A
| 0 | 0 | 391480632 | 35247931 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.DepthKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.RvalidKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.WreadyKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_instr_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_pc_mismatch_alert_o_assert_signals.AssertConnected_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.g_rf_ecc_err_comb_assert_signals.AssertConnected_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A
| 0 | 0 | 391480632 | 113 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A
| 0 | 0 | 391480632 | 189 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.DontExceeedMaxReqs
| 0 | 0 | 391480632 | 33426343 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.DontExceeedMaxReqs
| 0 | 0 | 391480632 | 45902962 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_cmd_intg_gen.PayMaxWidthCheck_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk.PayLoadWidthCheck
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.Priority_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 391480632 | 1032 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputDiffFromPrev_A
| 0 | 0 | 390830296 | 38354234 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.DataOutputValid_A
| 0 | 0 | 391480632 | 3808 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 391480632 | 3808 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 391480632 | 3808 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 391480632 | 3808 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 391480632 | 3808 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckHotOne_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.CheckNGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesReady_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GntImpliesValid_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.GrantKnown_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IdxKnown_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.IndexIsCorrect_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.Priority_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReadyAndValidImplyGrant_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqAndReadyImplyGrant_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ReqImpliesValid_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.ValidKnown_A
| 0 | 0 | 391480632 | 382055842 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region.gen_data_port_assertion.DataFlow_A
| 0 | 0 | 391480632 | 4406 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.OutputsKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync.gen_flops.OutputDelay_A
| 0 | 0 | 391480632 | 391370696 | 0 | 2871 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
| 0 | 0 | 391480632 | 27 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
| 0 | 0 | 391480632 | 27 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckAckNeedsReq
| 0 | 0 | 97800061 | 27 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data.u_prim_sync_reqack.SyncReqAckHoldReq
| 0 | 0 | 391480632 | 27 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.OutputsKnown_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync.gen_flops.OutputDelay_A
| 0 | 0 | 391480632 | 391370696 | 0 | 2871 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.en2addrHit
| 0 | 0 | 478502334 | 37099 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.reAfterRv
| 0 | 0 | 478502334 | 37099 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.rePulse
| 0 | 0 | 478502334 | 28669 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.NotOverflowed_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DataKnown_A
| 0 | 0 | 478502334 | 89423 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.DepthKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.RvalidKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.WreadyKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DataKnown_A
| 0 | 0 | 478502334 | 92421 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.DepthKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.RvalidKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.WreadyKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 478502334 | 49028 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 478502334 | 49028 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A
| 0 | 0 | 478502334 | 40395 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A
| 0 | 0 | 478502334 | 43393 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A
| 0 | 0 | 478502334 | 478383471 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.maxN
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.wePulse
| 0 | 0 | 478502334 | 8430 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.DataWidthCheck_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen.PayLoadWidthCheck
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 391480632 | 5 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.Irq0Tied_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.IrqKnownO_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.MsipKnownO_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlAReadyKnownO_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.TlDValidKnownO_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_irq_id_known[0].IrqIdKnownO_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputationInvalid_A
| 0 | 0 | 391480632 | 388981557 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxComputation_A
| 0 | 0 | 391480632 | 2396413 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputationInvalid_A
| 0 | 0 | 391480632 | 388981557 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.MaxIndexComputation_A
| 0 | 0 | 391480632 | 2396413 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.NumSources_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree.ValidInImpliesValidOut_A
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Claim
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.onehot0Complete
| 0 | 0 | 391480632 | 391377970 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.en2addrHit
| 0 | 0 | 478502334 | 211734 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.reAfterRv
| 0 | 0 | 478502334 | 211734 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.rePulse
| 0 | 0 | 478502334 | 134430 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 2875 | 2875 | 0 | 0 |
|
tb.dut.top_earlgrey.u_rv_plic.u_reg.wePulse
| 0 | 0 | 478502334 | 77304 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 97800061 | 2 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.NumAlertsMatch_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr.IntrTKind_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr.IntrTKind_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.en2addrHit
| 0 | 0 | 97800061 | 2229 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.reAfterRv
| 0 | 0 | 97800061 | 2229 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.rePulse
| 0 | 0 | 97800061 | 1955 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.wePulse
| 0 | 0 | 97800061 | 274 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
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tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|
tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic.AnalogNoScan_A
| 0 | 0 | 965 | 965 | 0 | 0 |
|