Unified Coverage Report :: Group Instance : sensor_ctrl

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T36	1	T50	1	T105	1
small_delay	911	1		T35	1	T258	1	T116	1
zero	689	1		T37	1	T257	1	T259	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T36	1	T50	1	T105	1
small_delay	611	1		T35	1	T116	1	T372	1
zero	689	1		T37	1	T257	1	T259	1