Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	506	1			T35	3		T259	1		T424	1
all_values[1]	514	1			T35	5		T424	1		T387	1
all_values[2]	525	1			T35	4		T259	2		T387	2
all_values[3]	516	1			T35	2		T259	3		T170	1
all_values[4]	491	1			T35	2		T259	1		T423	1
all_values[5]	482	1			T35	2		T259	1		T114	2
all_values[6]	525	1			T35	2		T259	3		T114	1
all_values[7]	510	1			T259	1		T359	1		T115	2
all_values[8]	519	1			T35	1		T170	1		T359	1
all_values[9]	527	1			T35	3		T259	1		T424	2
all_values[10]	552	1			T35	2		T170	1		T114	1
all_values[11]	519	1			T170	1		T359	1		T427	1
all_values[12]	499	1			T35	1		T359	1		T427	1
all_values[13]	519	1			T423	1		T114	1		T427	5
all_values[14]	490	1			T35	1		T259	2		T423	1
all_values[15]	472	1			T35	3		T259	2		T170	1
all_values[16]	492	1			T35	2		T170	1		T114	1
all_values[17]	508	1			T35	3		T259	1		T384	1
all_values[18]	532	1			T35	1		T259	2		T384	1
all_values[19]	519	1			T35	2		T114	1		T115	2
all_values[20]	527	1			T259	1		T359	1		T427	1
all_values[21]	499	1			T35	2		T259	1		T427	3
all_values[22]	467	1			T259	1		T114	1		T387	1
all_values[23]	536	1			T35	2		T259	2		T170	2
all_values[24]	521	1			T35	2		T259	1		T424	1
all_values[25]	492	1			T259	1		T114	2		T431	2
all_values[26]	498	1			T35	2		T259	2		T115	2
all_values[27]	517	1			T35	2		T387	1		T115	2
all_values[28]	539	1			T35	2		T423	1		T115	1
all_values[29]	495	1			T427	1		T115	1		T562	6
all_values[30]	542	1			T35	1		T114	1		T115	1
all_values[31]	500	1			T35	2		T259	1		T170	1
all_values[32]	491	1			T35	2		T259	2		T423	1
all_values[33]	514	1			T35	3		T259	1		T427	4
all_values[34]	507	1			T35	3		T170	3		T424	1
all_values[35]	529	1			T170	1		T114	1		T424	1
all_values[36]	517	1			T387	1		T431	2		T427	1
all_values[37]	504	1			T35	3		T259	1		T114	1
all_values[38]	500	1			T259	2		T387	1		T359	1
all_values[39]	523	1			T35	1		T424	1		T384	1
all_values[40]	514	1			T35	1		T170	1		T114	1
all_values[41]	495	1			T35	1		T259	1		T387	1
all_values[42]	479	1			T35	1		T170	1		T562	7
all_values[43]	520	1			T35	1		T259	1		T423	1
all_values[44]	503	1			T35	4		T259	1		T170	1
all_values[45]	503	1			T35	1		T387	1		T384	2
all_values[46]	512	1			T35	1		T114	1		T384	1
all_values[47]	547	1			T35	2		T424	1		T427	1
all_values[48]	475	1			T35	2		T259	1		T170	1
all_values[49]	476	1			T431	1		T427	1		T562	6