Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3757	1			T35	25		T169	1		T170	2
all_values[1]	3736	1			T35	19		T170	1		T417	2
all_values[2]	3648	1			T35	18		T169	2		T170	1
all_values[3]	3822	1			T35	20		T169	2		T170	1
all_values[4]	3647	1			T35	24		T169	1		T417	2
all_values[5]	3800	1			T35	20		T169	2		T170	1
all_values[6]	3689	1			T35	23		T170	1		T417	2
all_values[7]	3646	1			T35	20		T114	4		T427	5
all_values[8]	3655	1			T35	12		T170	2		T417	1
all_values[9]	3719	1			T35	22		T417	1		T114	7
all_values[10]	3803	1			T35	24		T169	2		T170	1
all_values[11]	3714	1			T35	23		T169	1		T170	3
all_values[12]	3710	1			T35	37		T169	1		T170	3
all_values[13]	3748	1			T35	21		T169	1		T170	1
all_values[14]	3812	1			T35	22		T170	1		T417	1
all_values[15]	3684	1			T35	24		T170	1		T417	1
all_values[16]	3751	1			T35	27		T169	1		T170	1
all_values[17]	3596	1			T35	18		T170	1		T417	2
all_values[18]	3688	1			T35	14		T169	3		T417	2
all_values[19]	3821	1			T35	20		T170	2		T114	7
all_values[20]	3774	1			T35	21		T169	1		T170	2
all_values[21]	3577	1			T35	20		T169	2		T170	1
all_values[22]	3680	1			T35	17		T169	2		T170	3
all_values[23]	3678	1			T35	24		T169	1		T170	3
all_values[24]	3657	1			T35	22		T170	1		T417	1
all_values[25]	3653	1			T35	14		T169	2		T170	1
all_values[26]	3656	1			T35	17		T169	1		T417	2
all_values[27]	3728	1			T35	23		T169	1		T170	3
all_values[28]	3704	1			T35	21		T169	1		T417	1
all_values[29]	3754	1			T35	22		T170	2		T417	1
all_values[30]	3804	1			T35	30		T417	1		T114	10
all_values[31]	3723	1			T35	25		T169	2		T170	1
all_values[32]	3648	1			T35	18		T169	1		T170	1
all_values[33]	3683	1			T35	21		T169	1		T170	1
all_values[34]	3701	1			T35	22		T170	2		T417	2
all_values[35]	3787	1			T35	21		T169	1		T170	1
all_values[36]	3726	1			T35	25		T169	2		T417	1
all_values[37]	3771	1			T35	22		T170	1		T114	6
all_values[38]	3691	1			T35	21		T169	2		T170	2
all_values[39]	3773	1			T35	21		T417	3		T114	4
all_values[40]	3806	1			T35	22		T170	4		T417	3
all_values[41]	3511	1			T35	20		T169	1		T417	2
all_values[42]	3747	1			T35	25		T169	3		T170	1
all_values[43]	3743	1			T35	21		T169	1		T170	1
all_values[44]	3804	1			T35	21		T169	3		T170	2
all_values[45]	3688	1			T35	21		T169	1		T170	3
all_values[46]	3774	1			T35	17		T170	1		T114	5
all_values[47]	3651	1			T35	19		T169	2		T170	2
all_values[48]	3745	1			T35	20		T169	1		T170	1
all_values[49]	3650	1			T35	17		T417	2		T114	5
all_values[50]	3699	1			T35	23		T169	1		T170	2
all_values[51]	3711	1			T35	14		T169	2		T417	1
all_values[52]	3668	1			T35	20		T169	1		T170	6
all_values[53]	3644	1			T35	18		T169	1		T170	1
all_values[54]	3800	1			T35	25		T170	1		T417	2
all_values[55]	3692	1			T35	24		T169	1		T170	3
all_values[56]	3705	1			T35	12		T169	1		T170	1
all_values[57]	3604	1			T35	24		T169	1		T170	4
all_values[58]	3739	1			T35	24		T170	1		T114	8
all_values[59]	3750	1			T35	17		T170	3		T417	1
all_values[60]	3760	1			T35	26		T169	1		T170	2
all_values[61]	3640	1			T35	19		T170	1		T417	1
all_values[62]	3721	1			T35	23		T169	1		T170	1
all_values[63]	3756	1			T35	27		T169	1		T170	3