Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3527980	1			T77	1088		T78	115		T79	122
values[2]	715253	1			T77	310		T78	23		T79	44
values[3]	98741	1			T77	2		T78	11		T79	1
values[4]	51112	1			T113	3		T474	88		T391	19
values[5]	34305	1			T113	3		T474	77		T391	19
values[6]	25845	1			T113	3		T474	65		T391	20
values[7]	20987	1			T113	3		T474	100		T391	19
values[8]	18028	1			T113	3		T474	106		T391	19
values[9]	15854	1			T113	3		T474	127		T391	19
values[10]	14620	1			T113	3		T474	129		T391	19
values[11]	13658	1			T113	3		T474	77		T391	19
values[12]	12763	1			T113	3		T474	38		T391	19
values[13]	12083	1			T113	3		T474	61		T391	19
values[14]	11628	1			T113	3		T474	79		T391	21
values[15]	11072	1			T113	3		T474	116		T391	19
values[16]	10657	1			T113	3		T474	95		T391	19
values[17]	9932	1			T113	3		T474	67		T391	19
values[18]	9346	1			T113	3		T474	77		T391	19
values[19]	9028	1			T113	3		T474	60		T391	20
values[20]	8925	1			T113	3		T474	72		T391	20
values[21]	8638	1			T113	3		T474	90		T391	19
values[22]	8396	1			T113	3		T474	74		T391	19
values[23]	8059	1			T113	3		T474	74		T391	19
values[24]	7973	1			T113	3		T474	77		T391	19
values[25]	7823	1			T113	3		T474	85		T391	19
values[26]	7754	1			T113	3		T474	86		T391	19
values[27]	7153	1			T113	3		T474	62		T391	19
values[28]	6738	1			T113	3		T474	44		T391	19
values[29]	6411	1			T113	3		T474	44		T391	20
values[30]	5693	1			T113	3		T474	41		T391	19
values[31]	5388	1			T113	3		T474	44		T391	19
values[32]	5063	1			T113	3		T474	39		T391	19
values[33]	4816	1			T113	3		T474	16		T391	19
values[34]	4476	1			T113	3		T474	8		T391	20
values[35]	4301	1			T113	3		T474	9		T391	19
values[36]	4093	1			T113	3		T474	8		T391	19
values[37]	3870	1			T113	3		T474	3		T391	19
values[38]	3573	1			T113	3		T474	2		T391	19
values[39]	3475	1			T113	3		T474	4		T391	19
values[40]	3370	1			T113	3		T474	5		T391	20
values[41]	3328	1			T113	3		T474	7		T391	20
values[42]	3151	1			T113	3		T474	2		T391	19
values[43]	3108	1			T113	3		T474	1		T391	19
values[44]	3200	1			T113	3		T474	3		T391	20
values[45]	3076	1			T113	3		T474	1		T391	19
values[46]	2972	1			T113	3		T474	2		T391	19
values[47]	2882	1			T113	3		T474	1		T391	19
values[48]	2829	1			T113	3		T474	4		T391	19
values[49]	2822	1			T113	3		T474	4		T391	20
values[50]	2844	1			T113	3		T474	3		T391	19
values[51]	2859	1			T113	3		T474	6		T391	20
values[52]	2731	1			T113	3		T474	4		T391	19
values[53]	2710	1			T113	3		T474	7		T391	19
values[54]	2598	1			T113	3		T474	2		T391	19
values[55]	2654	1			T113	3		T474	2		T391	19
values[56]	2459	1			T113	4		T474	5		T391	19
values[57]	2503	1			T113	3		T391	19		T499	7
values[58]	2476	1			T113	3		T391	19		T499	5
values[59]	2474	1			T113	3		T391	20		T499	4
values[60]	2527	1			T113	3		T391	20		T499	13
values[61]	2758	1			T113	3		T391	20		T499	7
values[62]	4647	1			T113	3		T391	19		T499	15
values[63]	15920	1			T113	3		T391	22		T499	20
values[64]	212706	1			T113	526		T391	3669		T499	44

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4516086	1			T77	1101		T78	100		T79	110
values[2]	754996	1			T77	338		T78	26		T79	29
values[3]	73342	1			T77	8		T78	6		T79	9
values[4]	13254	1			T78	4		T79	1		T113	16
values[5]	5144	1			T78	1		T79	1		T113	4
values[6]	2871	1			T113	1		T391	9		T443	13
values[7]	2182	1			T391	3		T443	9		T421	2
values[8]	1795	1			T391	3		T443	16		T421	1
values[9]	1581	1			T391	2		T443	16		T689	2
values[10]	1426	1			T391	2		T443	8		T689	1
values[11]	1321	1			T391	2		T443	2		T689	1
values[12]	1272	1			T391	2		T443	2		T689	1
values[13]	1229	1			T391	2		T443	2		T689	1
values[14]	1049	1			T391	2		T443	3		T689	1
values[15]	994	1			T391	2		T443	4		T689	1
values[16]	920	1			T391	2		T443	2		T689	1
values[17]	862	1			T391	2		T443	3		T689	1
values[18]	794	1			T391	2		T443	4		T689	1
values[19]	802	1			T391	2		T443	9		T689	1
values[20]	786	1			T391	2		T443	6		T689	1
values[21]	763	1			T391	2		T443	1		T689	1
values[22]	724	1			T391	2		T443	2		T689	1
values[23]	736	1			T391	2		T443	2		T689	1
values[24]	677	1			T391	2		T443	8		T689	1
values[25]	659	1			T391	2		T443	11		T689	1
values[26]	692	1			T391	2		T443	6		T689	1
values[27]	711	1			T391	2		T443	6		T689	1
values[28]	654	1			T391	2		T443	7		T689	1
values[29]	637	1			T391	2		T443	5		T689	1
values[30]	596	1			T391	2		T443	5		T689	1
values[31]	564	1			T391	2		T443	10		T689	1
values[32]	584	1			T391	2		T443	8		T689	1
values[33]	557	1			T391	2		T443	3		T689	1
values[34]	515	1			T391	2		T443	15		T689	1
values[35]	506	1			T391	2		T443	4		T689	1
values[36]	473	1			T391	2		T443	4		T689	1
values[37]	466	1			T391	2		T443	4		T689	1
values[38]	491	1			T391	2		T443	2		T689	1
values[39]	464	1			T391	2		T443	3		T689	1
values[40]	454	1			T391	2		T443	3		T689	1
values[41]	441	1			T391	2		T443	6		T689	1
values[42]	433	1			T391	2		T443	6		T689	1
values[43]	456	1			T391	2		T443	4		T689	1
values[44]	432	1			T391	2		T443	2		T689	1
values[45]	429	1			T391	2		T443	4		T689	1
values[46]	393	1			T391	2		T443	8		T689	1
values[47]	417	1			T391	2		T443	4		T689	1
values[48]	397	1			T391	2		T443	1		T689	1
values[49]	412	1			T391	2		T689	1		T422	8
values[50]	431	1			T391	2		T689	1		T422	6
values[51]	390	1			T391	2		T689	1		T422	6
values[52]	397	1			T391	2		T689	1		T422	5
values[53]	394	1			T391	2		T689	1		T422	16
values[54]	372	1			T391	2		T689	1		T422	10
values[55]	383	1			T391	2		T689	1		T422	12
values[56]	378	1			T391	2		T689	1		T422	5
values[57]	368	1			T391	2		T689	1		T422	8
values[58]	352	1			T391	2		T689	1		T422	11
values[59]	341	1			T391	3		T689	1		T422	6
values[60]	343	1			T391	2		T689	1		T422	5
values[61]	406	1			T391	2		T689	2		T422	3
values[62]	723	1			T391	2		T689	1		T422	12
values[63]	3425	1			T391	2		T689	1		T422	32
values[64]	24338	1			T391	382		T689	160		T422	44

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	539192	1			T77	10		T78	1		T79	2
values[2]	2509994	1			T77	1129		T78	132		T79	15
values[3]	1102456	1			T77	269		T78	57		T79	92
values[4]	140307	1			T78	1		T79	1		T113	3
values[5]	71247	1			T78	1		T113	3		T474	81
values[6]	46823	1			T113	3		T474	83		T504	1
values[7]	34193	1			T113	3		T474	95		T391	19
values[8]	26846	1			T113	3		T474	55		T391	19
values[9]	21871	1			T113	3		T474	73		T391	19
values[10]	19184	1			T113	3		T474	104		T391	19
values[11]	17416	1			T113	3		T474	83		T391	19
values[12]	16080	1			T113	3		T474	102		T391	19
values[13]	15006	1			T113	3		T474	96		T391	19
values[14]	14235	1			T113	3		T474	93		T391	19
values[15]	13571	1			T113	3		T474	103		T391	19
values[16]	13112	1			T113	3		T474	73		T391	19
values[17]	12314	1			T113	3		T474	87		T391	19
values[18]	11958	1			T113	3		T474	102		T391	21
values[19]	11234	1			T113	3		T474	84		T391	19
values[20]	10728	1			T113	3		T474	67		T391	19
values[21]	10517	1			T113	3		T474	66		T391	19
values[22]	9816	1			T113	3		T474	68		T391	19
values[23]	9397	1			T113	3		T474	75		T391	19
values[24]	9030	1			T113	3		T474	68		T391	19
values[25]	8593	1			T113	3		T474	69		T391	20
values[26]	8631	1			T113	3		T474	63		T391	20
values[27]	8255	1			T113	3		T474	44		T391	19
values[28]	7642	1			T113	3		T474	35		T391	19
values[29]	7081	1			T113	3		T474	69		T391	19
values[30]	6656	1			T113	3		T474	45		T391	19
values[31]	6170	1			T113	3		T474	52		T391	19
values[32]	5809	1			T113	3		T474	61		T391	19
values[33]	5407	1			T113	3		T474	43		T391	19
values[34]	5054	1			T113	3		T474	36		T391	19
values[35]	4663	1			T113	3		T474	32		T391	19
values[36]	4363	1			T113	3		T474	20		T391	19
values[37]	4167	1			T113	3		T474	22		T391	19
values[38]	4026	1			T113	3		T474	29		T391	19
values[39]	3923	1			T113	3		T474	30		T391	19
values[40]	3805	1			T113	3		T474	20		T391	19
values[41]	3682	1			T113	3		T474	25		T391	19
values[42]	3682	1			T113	3		T474	27		T391	20
values[43]	3604	1			T113	3		T474	16		T391	19
values[44]	3514	1			T113	3		T474	15		T391	20
values[45]	3470	1			T113	3		T474	8		T391	19
values[46]	3420	1			T113	3		T474	4		T391	19
values[47]	3421	1			T113	3		T474	11		T391	20
values[48]	3417	1			T113	3		T474	7		T391	19
values[49]	3418	1			T113	4		T474	7		T391	19
values[50]	3349	1			T113	3		T474	8		T391	19
values[51]	3310	1			T113	3		T474	6		T391	19
values[52]	3159	1			T113	3		T474	11		T391	19
values[53]	3006	1			T113	3		T474	3		T391	19
values[54]	2985	1			T113	3		T474	12		T391	19
values[55]	3017	1			T113	3		T474	6		T391	19
values[56]	2963	1			T113	3		T474	7		T391	20
values[57]	2750	1			T113	4		T474	11		T391	19
values[58]	2693	1			T113	3		T474	7		T391	19
values[59]	2692	1			T113	3		T474	7		T391	19
values[60]	2646	1			T113	3		T474	11		T391	19
values[61]	2790	1			T113	3		T474	4		T391	20
values[62]	4425	1			T113	3		T474	9		T391	19
values[63]	17870	1			T113	26		T474	2		T391	21
values[64]	200230	1			T113	571		T391	3326		T499	73