Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2245321	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27565861

1

T1

21747

T2

3199

T3

8296

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19511014	1			T1	9322		T2	637		T3	2622
values[0x0]	8443955	1			T1	12425		T2	2562		T3	5674
values[0x1]	1856213	1			T1	684		T2	82		T3	403

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	547972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29263210

1

T1

22431

T2

3281

T3

8699

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13836255	1			T1	11216		T2	1641		T3	4350
valid_sources[0x01]	13835818	1			T1	11215		T2	1640		T3	4349
valid_sources[0x02]	34188	1			T22	3		T81	13		T112	28
valid_sources[0x03]	34071	1			T46	4		T22	1		T81	16
valid_sources[0x04]	34430	1			T236	1		T81	22		T112	92
valid_sources[0x05]	34328	1			T236	1		T81	11		T112	42
valid_sources[0x06]	35600	1			T81	14		T112	11		T658	2
valid_sources[0x07]	35090	1			T22	1		T402	2		T81	13
valid_sources[0x08]	34561	1			T46	6		T22	1		T403	5
valid_sources[0x09]	34104	1			T22	1		T81	23		T112	20
valid_sources[0x0a]	35047	1			T46	3		T22	2		T81	16
valid_sources[0x0b]	34649	1			T402	3		T81	7		T112	1
valid_sources[0x0c]	34103	1			T236	1		T81	18		T112	27
valid_sources[0x0d]	34837	1			T236	1		T81	17		T112	19
valid_sources[0x0e]	34601	1			T236	1		T81	13		T112	46
valid_sources[0x0f]	34479	1			T22	2		T236	1		T81	15
valid_sources[0x10]	34116	1			T22	2		T236	2		T81	16
valid_sources[0x11]	34350	1			T22	1		T81	16		T658	2
valid_sources[0x12]	34558	1			T81	10		T112	2		T658	2
valid_sources[0x13]	36036	1			T22	1		T402	3		T236	1
valid_sources[0x14]	34392	1			T46	3		T402	7		T403	1
valid_sources[0x15]	34513	1			T81	10		T112	18		T658	1
valid_sources[0x16]	34152	1			T402	1		T81	11		T112	49
valid_sources[0x17]	33885	1			T46	4		T402	1		T403	1
valid_sources[0x18]	35520	1			T236	2		T81	24		T112	29
valid_sources[0x19]	34856	1			T81	15		T112	15		T658	5
valid_sources[0x1a]	33880	1			T22	1		T403	1		T81	10
valid_sources[0x1b]	34603	1			T402	1		T236	2		T81	14
valid_sources[0x1c]	34289	1			T403	5		T81	18		T112	12
valid_sources[0x1d]	34693	1			T22	1		T81	25		T112	27
valid_sources[0x1e]	34243	1			T46	4		T81	16		T112	20
valid_sources[0x1f]	35303	1			T46	2		T403	4		T236	1
valid_sources[0x20]	33641	1			T81	13		T112	42		T658	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18901519

1

T1

9322

T2

637

T3

2622

values[0x0]

all_enables

biggest_size

8406225

1

T1

12425

T2

2562

T3

5674

values[0x1]

all_enables

biggest_size

258117

1

T46

17

T47

19

T22

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2691708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

425386

1

T77

2

T78

15

T79

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1056429	1			T77	20		T78	46		T79	59
values[0x0]	1006071	1			T77	2		T78	46		T79	51
values[0x1]	1054594	1			T77	26		T78	57		T79	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2083959	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1033135

1

T77

20

T78

44

T79

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	47727	1			T77	1		T113	10		T82	3
valid_sources[0x01]	47995	1			T79	6		T113	7		T82	3
valid_sources[0x02]	48535	1			T79	2		T113	9		T82	5
valid_sources[0x03]	49329	1			T78	2		T79	2		T113	10
valid_sources[0x04]	48320	1			T77	1		T78	3		T113	12
valid_sources[0x05]	48762	1			T113	6		T82	5		T156	12
valid_sources[0x06]	47973	1			T79	1		T113	15		T82	2
valid_sources[0x07]	48081	1			T77	1		T78	1		T79	3
valid_sources[0x08]	48582	1			T78	2		T79	6		T113	13
valid_sources[0x09]	49470	1			T77	2		T79	3		T113	9
valid_sources[0x0a]	48948	1			T77	1		T79	1		T113	12
valid_sources[0x0b]	48955	1			T77	1		T78	12		T79	2
valid_sources[0x0c]	48640	1			T77	1		T79	2		T113	8
valid_sources[0x0d]	48407	1			T77	1		T79	2		T113	10
valid_sources[0x0e]	48713	1			T77	1		T78	6		T79	2
valid_sources[0x0f]	48717	1			T79	4		T113	13		T82	1
valid_sources[0x10]	49188	1			T77	1		T78	3		T79	4
valid_sources[0x11]	49236	1			T77	1		T79	2		T113	11
valid_sources[0x12]	48772	1			T79	6		T113	12		T82	2
valid_sources[0x13]	48560	1			T77	2		T78	2		T79	1
valid_sources[0x14]	48498	1			T77	1		T79	5		T113	18
valid_sources[0x15]	47665	1			T77	1		T78	11		T79	2
valid_sources[0x16]	48626	1			T77	2		T79	4		T113	13
valid_sources[0x17]	48477	1			T77	1		T113	9		T156	20
valid_sources[0x18]	48293	1			T77	1		T78	3		T79	1
valid_sources[0x19]	48760	1			T78	19		T79	2		T113	11
valid_sources[0x1a]	47160	1			T78	7		T79	4		T113	9
valid_sources[0x1b]	49025	1			T113	14		T82	4		T156	35
valid_sources[0x1c]	48807	1			T78	7		T79	2		T113	9
valid_sources[0x1d]	48524	1			T77	2		T79	1		T113	10
valid_sources[0x1e]	49108	1			T77	2		T78	15		T79	3
valid_sources[0x1f]	47399	1			T77	1		T79	5		T113	8
valid_sources[0x20]	48761	1			T78	5		T79	7		T113	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44773

1

T79

3

T113

11

T82

2

values[0x0]

all_enables

biggest_size

335866

1

T77

1

T78

15

T79

12

values[0x1]

all_enables

biggest_size

44747

1

T77

1

T79

3

T113

12

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2866294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

467693

1

T77

6

T78

17

T79

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1142203	1			T77	30		T78	42		T79	58
values[0x0]	1049391	1			T77	3		T78	48		T79	40
values[0x1]	1142393	1			T77	33		T78	47		T79	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2198792	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135195

1

T77

26

T78

40

T79

65

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52751	1			T77	2		T78	1		T113	10
valid_sources[0x01]	51363	1			T78	1		T113	13		T82	12
valid_sources[0x02]	51438	1			T78	1		T113	19		T156	12
valid_sources[0x03]	52531	1			T78	3		T79	1		T113	9
valid_sources[0x04]	52838	1			T77	1		T78	2		T113	14
valid_sources[0x05]	52066	1			T78	4		T79	2		T113	12
valid_sources[0x06]	51575	1			T77	1		T79	2		T113	10
valid_sources[0x07]	51972	1			T77	1		T78	5		T79	10
valid_sources[0x08]	51796	1			T78	1		T113	14		T156	23
valid_sources[0x09]	51502	1			T78	1		T79	4		T113	13
valid_sources[0x0a]	51754	1			T77	1		T78	1		T79	3
valid_sources[0x0b]	51662	1			T77	1		T78	4		T113	10
valid_sources[0x0c]	53318	1			T78	2		T79	1		T113	10
valid_sources[0x0d]	51508	1			T78	1		T113	14		T156	21
valid_sources[0x0e]	51872	1			T78	3		T113	4		T156	18
valid_sources[0x0f]	51678	1			T77	4		T78	1		T113	15
valid_sources[0x10]	52602	1			T77	1		T78	7		T113	16
valid_sources[0x11]	51778	1			T77	2		T79	4		T113	11
valid_sources[0x12]	52453	1			T77	1		T113	17		T156	16
valid_sources[0x13]	52037	1			T77	2		T78	3		T79	1
valid_sources[0x14]	51537	1			T77	1		T113	4		T156	29
valid_sources[0x15]	51185	1			T77	3		T78	2		T113	12
valid_sources[0x16]	51135	1			T79	15		T113	7		T82	4
valid_sources[0x17]	52168	1			T77	2		T78	2		T113	12
valid_sources[0x18]	51908	1			T77	1		T79	1		T113	15
valid_sources[0x19]	52335	1			T77	1		T78	3		T79	2
valid_sources[0x1a]	50604	1			T78	1		T79	3		T113	19
valid_sources[0x1b]	52111	1			T77	1		T78	2		T79	2
valid_sources[0x1c]	53010	1			T77	3		T78	1		T113	9
valid_sources[0x1d]	51758	1			T78	2		T113	11		T156	16
valid_sources[0x1e]	50650	1			T77	1		T78	2		T79	4
valid_sources[0x1f]	52883	1			T77	2		T113	6		T156	24
valid_sources[0x20]	51743	1			T78	2		T79	9		T113	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49035

1

T77

2

T79

3

T113

7

values[0x0]

all_enables

biggest_size

369696

1

T77

1

T78

17

T79

14

values[0x1]

all_enables

biggest_size

48962

1

T77

3

T79

4

T113

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2699422	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

426888

1

T77

6

T78

17

T79

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1057911	1			T77	20		T78	77		T79	32
values[0x0]	1008326	1			T77	2		T78	53		T79	38
values[0x1]	1060073	1			T77	36		T78	62		T79	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2089509	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1036801

1

T77

24

T78

59

T79

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48955	1			T77	1		T79	2		T113	8
valid_sources[0x01]	48611	1			T79	3		T113	19		T82	3
valid_sources[0x02]	48992	1			T77	1		T78	2		T113	14
valid_sources[0x03]	48802	1			T79	5		T113	14		T82	2
valid_sources[0x04]	48041	1			T78	1		T79	5		T113	14
valid_sources[0x05]	49970	1			T77	1		T78	5		T113	15
valid_sources[0x06]	48389	1			T77	1		T79	5		T113	15
valid_sources[0x07]	47528	1			T78	2		T113	11		T82	5
valid_sources[0x08]	48733	1			T77	2		T78	2		T113	13
valid_sources[0x09]	49436	1			T78	1		T113	9		T82	2
valid_sources[0x0a]	48849	1			T78	3		T113	9		T82	2
valid_sources[0x0b]	48738	1			T78	1		T113	14		T82	7
valid_sources[0x0c]	48204	1			T77	2		T79	1		T113	12
valid_sources[0x0d]	47897	1			T77	2		T78	6		T113	8
valid_sources[0x0e]	48630	1			T77	1		T78	3		T79	1
valid_sources[0x0f]	48808	1			T78	4		T79	3		T113	14
valid_sources[0x10]	48604	1			T77	1		T78	1		T113	11
valid_sources[0x11]	48773	1			T78	1		T113	10		T82	1
valid_sources[0x12]	49543	1			T77	1		T78	4		T113	11
valid_sources[0x13]	48791	1			T78	5		T79	9		T113	12
valid_sources[0x14]	49019	1			T77	3		T78	2		T113	12
valid_sources[0x15]	48999	1			T77	1		T78	2		T113	11
valid_sources[0x16]	49168	1			T78	3		T113	13		T82	4
valid_sources[0x17]	47828	1			T77	2		T78	1		T79	2
valid_sources[0x18]	48658	1			T78	4		T79	3		T113	14
valid_sources[0x19]	49107	1			T77	1		T113	11		T82	3
valid_sources[0x1a]	48392	1			T77	1		T78	2		T113	9
valid_sources[0x1b]	49390	1			T77	1		T78	1		T79	1
valid_sources[0x1c]	49510	1			T77	2		T78	3		T113	9
valid_sources[0x1d]	49686	1			T78	5		T113	16		T82	1
valid_sources[0x1e]	49267	1			T77	4		T78	5		T113	9
valid_sources[0x1f]	49368	1			T78	2		T79	1		T113	13
valid_sources[0x20]	48822	1			T77	2		T78	3		T113	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44766

1

T77

1

T78

1

T79

1

values[0x0]

all_enables

biggest_size

337141

1

T78

15

T79

13

T113

59

values[0x1]

all_enables

biggest_size

44981

1

T77

5

T78

1

T79

1