Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	100.00			100.00
tb.dut.top_earlgrey.u_i2c1	100.00			100.00
tb.dut.top_earlgrey.u_i2c2	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	328	328	100.00
Total Bits 0->1	164	164	100.00
Total Bits 1->0	164	164	100.00

Ports	48	48	100.00
Port Bits	328	328	100.00
Port Bits 0->1	164	164	100.00
Port Bits 1->0	164	164	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T184,T180,T300	Yes	T184,T180,T300	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T184,T180,T300	Yes	T184,T180,T300	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T65,T184,T180	Yes	T65,T184,T180	INPUT
tl_o.a_ready	Yes	Yes	T65,T184,T180	Yes	T65,T184,T180	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T184,T180,T300	Yes	T184,T180,T300	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T184,T180	Yes	T65,T184,T180	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T184,T180	Yes	T65,T184,T180	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T184,*T180,*T300	Yes	T184,T180,T300	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T65,T184,T180	Yes	T65,T184,T180	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T680,T84	Yes	T65,T680,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T679,T197	Yes	T84,T197,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T197,T85	Yes	T84,T679,T197	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T680,T84	Yes	T65,T680,T84	OUTPUT
cio_scl_i	Yes	Yes	T184,T180,T181	Yes	T184,T180,T181	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T184,T313,T294	Yes	T184,T313,T294	OUTPUT
cio_sda_i	Yes	Yes	T184,T180,T181	Yes	T184,T180,T181	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T184,T180,T181	Yes	T184,T180,T181	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T184,T300,T313	Yes	T184,T300,T313	OUTPUT
intr_rx_threshold_o	Yes	Yes	T184,T300,T313	Yes	T184,T300,T313	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_nak_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_scl_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_unstable_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_cmd_complete_o	Yes	Yes	T184,T180,T300	Yes	T184,T180,T300	OUTPUT
intr_tx_stretch_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_tx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_acq_full_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_unexp_stop_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_host_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	324	324	100.00
Total Bits 0->1	162	162	100.00
Total Bits 1->0	162	162	100.00

Ports	48	48	100.00
Port Bits	324	324	100.00
Port Bits 0->1	162	162	100.00
Port Bits 1->0	162	162	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T180,T300,T181	Yes	T180,T300,T181	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T180,T300,T181	Yes	T180,T300,T181	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	INPUT
tl_o.a_ready	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T180,T300,T181	Yes	T180,T300,T181	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T113,*T156	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T180,*T300,*T181	Yes	T180,T300,T181	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T84,T197	Yes	T65,T84,T197	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T197,T85	Yes	T84,T197,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T197,T85	Yes	T84,T197,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T84,T197	Yes	T65,T84,T197	OUTPUT
cio_scl_i	Yes	Yes	T180,T181,T414	Yes	T180,T181,T414	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T312,T706,T707	Yes	T312,T706,T707	OUTPUT
cio_sda_i	Yes	Yes	T180,T181,T414	Yes	T180,T181,T414	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T180,T181,T414	Yes	T180,T181,T414	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T300,T298,T312	Yes	T300,T298,T312	OUTPUT
intr_rx_threshold_o	Yes	Yes	T300,T298,T312	Yes	T300,T298,T312	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_nak_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_scl_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_unstable_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_cmd_complete_o	Yes	Yes	T180,T300,T181	Yes	T180,T300,T181	OUTPUT
intr_tx_stretch_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_tx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_acq_full_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_unexp_stop_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_host_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	326	326	100.00
Total Bits 0->1	163	163	100.00
Total Bits 1->0	163	163	100.00

Ports	48	48	100.00
Port Bits	326	326	100.00
Port Bits 0->1	163	163	100.00
Port Bits 1->0	163	163	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	INPUT
tl_o.a_ready	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T77,*T156,*T404	Yes	T77,T78,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T184,*T300,*T298	Yes	T184,T300,T298	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T84,T679	Yes	T65,T84,T679	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T679,T197	Yes	T84,T197,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T197,T85	Yes	T84,T679,T197	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T84,T679	Yes	T65,T84,T679	OUTPUT
cio_scl_i	Yes	Yes	T184,T321,T322	Yes	T184,T321,T322	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T184,T321,T322	Yes	T184,T321,T322	OUTPUT
cio_sda_i	Yes	Yes	T184,T321,T322	Yes	T184,T321,T322	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T184,T321,T322	Yes	T184,T321,T322	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	OUTPUT
intr_rx_threshold_o	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_nak_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_scl_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_unstable_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_cmd_complete_o	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	OUTPUT
intr_tx_stretch_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_tx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_acq_full_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_unexp_stop_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_host_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	326	326	100.00
Total Bits 0->1	163	163	100.00
Total Bits 1->0	163	163	100.00

Ports	48	48	100.00
Port Bits	326	326	100.00
Port Bits 0->1	163	163	100.00
Port Bits 1->0	163	163	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	INPUT
tl_o.a_ready	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T77,*T78,*T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T300,*T313,*T294	Yes	T300,T313,T294	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T680,T84	Yes	T65,T680,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T197,T85	Yes	T84,T197,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T197,T85	Yes	T84,T197,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T680,T84	Yes	T65,T680,T84	OUTPUT
cio_scl_i	Yes	Yes	T313,T294,T415	Yes	T313,T294,T415	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T313,T294,T415	Yes	T313,T294,T415	OUTPUT
cio_sda_i	Yes	Yes	T313,T294,T415	Yes	T313,T294,T415	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T313,T294,T415	Yes	T313,T294,T415	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	OUTPUT
intr_rx_threshold_o	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	OUTPUT
intr_fmt_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_nak_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_scl_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_interference_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_sda_unstable_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_cmd_complete_o	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	OUTPUT
intr_tx_stretch_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_tx_overflow_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_acq_full_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_unexp_stop_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT
intr_host_timeout_o	Yes	Yes	T300,T298,T311	Yes	T300,T298,T311	OUTPUT

*Tests covering at least one bit in the range