Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_dm	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	82	82	100.00
Total Bits	906	906	100.00
Total Bits 0->1	453	453	100.00
Total Bits 1->0	453	453	100.00

Ports	82	82	100.00
Port Bits	906	906	100.00
Port Bits 0->1	453	453	100.00
Port Bits 1->0	453	453	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T3,T34,T5	Yes	T2,T3,T38	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T3,T34,T5	Yes	T2,T3,T38	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
ndmreset_req_o	Yes	Yes	T70,T188,T48	Yes	T70,T188,T48	OUTPUT
dmactive_o	Yes	Yes	T72,T80,T46	Yes	T67,T70,T71	OUTPUT
debug_req_o	Yes	Yes	T70,T188,T189	Yes	T70,T188,T189	OUTPUT
unavailable_i	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.d_ready	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T47,T77,T78	Yes	T47,T77,T78	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_address[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_address[20:2]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[21]	Yes	Yes	*T46,*T47,*T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_address[23:22]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[24]	Yes	Yes	*T46,*T47,*T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[30]	Yes	Yes	*T46,*T47,*T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_source[5:0]	Yes	Yes	*T46,*T47,T77	Yes	T46,T47,T77	INPUT
regs_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T46,T47,T78	Yes	T46,T47,T77	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	OUTPUT
regs_tl_d_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
regs_tl_d_o.d_source[5:0]	Yes	Yes	*T46,*T47,T77	Yes	T46,T47,T77	OUTPUT
regs_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
regs_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T46,*T47,*T77	Yes	T46,T47,T77	OUTPUT
regs_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T46,T47,T77	Yes	T46,T47,T77	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	INPUT
mem_tl_d_i.a_address[11:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
mem_tl_d_i.a_address[15:12]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_address[16]	Yes	Yes	*T70,*T46,*T188	Yes	T70,T46,T188	INPUT
mem_tl_d_i.a_address[31:17]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_source[5:0]	Yes	Yes	*T70,*T188,*T189	Yes	T70,T188,T189	INPUT
mem_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
mem_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T2,T3,T38	Yes	T2,T3,T38	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T2,T3,T38	Yes	T3,T34,T5	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T70,T188,T189	Yes	T70,T188,T189	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T2,T3,T38	Yes	T3,T34,T5	OUTPUT
mem_tl_d_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
mem_tl_d_o.d_source[5:0]	Yes	Yes	*T70,*T188,*T189	Yes	T70,T188,T189	OUTPUT
mem_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
mem_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T38	Yes	T3,T34,T5	OUTPUT
mem_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T70,T46,T188	Yes	T70,T46,T188	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T3,T34,T5	Yes	T2,T3,T38	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T67,T34	Yes	T2,T3,T38	OUTPUT
sba_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T3,T34,T5	Yes	T2,T3,T38	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T3,T34,T5	Yes	T2,T3,T38	OUTPUT
sba_tl_h_o.a_address[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_opcode[2:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T1,T3,T67	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T67,T71,T72	Yes	T67,T71,T72	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_source[5:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
sba_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T67,*T70,*T71	Yes	T67,T70,T71	INPUT
sba_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T46,T84	Yes	T59,T46,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T46,T84	Yes	T59,T46,T84	OUTPUT
jtag_i.tdi	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	INPUT
jtag_i.trst_n	Yes	Yes	T67,T71,T72	Yes	T67,T70,T71	INPUT
jtag_i.tms	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	INPUT
jtag_i.tck	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	INPUT
jtag_o.tdo_oe	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	OUTPUT
jtag_o.tdo	Yes	Yes	T67,T70,T71	Yes	T67,T70,T71	OUTPUT

*Tests covering at least one bit in the range