Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_165

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_166

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_167

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_168

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_169

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_170

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_171

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_172

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_173

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_174

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_175

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_176

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_177

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_178

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_179

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.97	100.00	99.90			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_165

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_165

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_165

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_166

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_166

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_166

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_167

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_167

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_167

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_168

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_168

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_168

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_169

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_169

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_169

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_170

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_170

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_170

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_171

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_171

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_171

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_172

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_172

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_172

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_173

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_173

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_173

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_174

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_174

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_174

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_175

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_175

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_175

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_176

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_176

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_176

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_177

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_177

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_177

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_178

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_178

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_178

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_179

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_179

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_179

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_0

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_0

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_0

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_1

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_1

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_1

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_2

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_2

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_2

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_3

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_3

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_3

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_4

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_4

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_4

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_5

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_5

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_5

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_6

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_6

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_6

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_7

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_7

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_7

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_8

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			MISSING_ELSE
64	1	1
65	1	1
72	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_8

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T54,T13

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ie0_0_e_8

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	64	2	2	100.00
IF	56	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	64	(wr_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T88,T54,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T88,T54,T13
0	0	Covered	T1,T2,T3