Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412404010	45309085	0	0
DepthKnown_A	412404010	412303536	0	0
RvalidKnown_A	412404010	412303536	0	0
WreadyKnown_A	412404010	412303536	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	45309085	0	0
T1	440458	55589	0	0
T2	61615	5984	0	0
T3	193036	16460	0	0
T34	387201	47461	0	0
T38	130956	15155	0	0
T43	685494	83777	0	0
T54	120738	89497	0	0
T67	70936	3456	0	0
T87	83489	8911	0	0
T88	80931	8373	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412404010	34704051	0	0
DepthKnown_A	412404010	412303536	0	0
RvalidKnown_A	412404010	412303536	0	0
WreadyKnown_A	412404010	412303536	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	34704051	0	0
T1	440458	43489	0	0
T2	61615	4136	0	0
T3	193036	12125	0	0
T34	387201	39268	0	0
T38	130956	11172	0	0
T43	685494	67054	0	0
T54	120738	85700	0	0
T67	70936	1864	0	0
T87	83489	7028	0	0
T88	80931	6364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412404010	33211070	0	0
DepthKnown_A	412404010	412303536	0	0
RvalidKnown_A	412404010	412303536	0	0
WreadyKnown_A	412404010	412303536	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	33211070	0	0
T1	440458	23158	0	0
T2	61615	3397	0	0
T3	193036	8946	0	0
T34	387201	23245	0	0
T38	130956	12231	0	0
T43	685494	135538	0	0
T54	120738	157289	0	0
T67	70936	464	0	0
T87	83489	5509	0	0
T88	80931	5054	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412404010	27663137	0	0
DepthKnown_A	412404010	412303536	0	0
RvalidKnown_A	412404010	412303536	0	0
WreadyKnown_A	412404010	412303536	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	27663137	0	0
T1	440458	22431	0	0
T2	61615	3281	0	0
T3	193036	8699	0	0
T34	387201	22791	0	0
T38	130956	11953	0	0
T43	685494	59654	0	0
T54	120738	157085	0	0
T67	70936	353	0	0
T87	83489	5383	0	0
T88	80931	4933	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	412303536	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496457362	85817	0	0
DepthKnown_A	496457362	496345304	0	0
RvalidKnown_A	496457362	496345304	0	0
WreadyKnown_A	496457362	496345304	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	85817	0	0
T1	440458	77	0	0
T2	61615	13	0	0
T3	193036	30	0	0
T34	387201	60	0	0
T38	130956	94	0	0
T43	685494	26	0	0
T54	120738	53	0	0
T67	70936	8	0	0
T87	83489	13	0	0
T88	80931	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496457362	88092	0	0
DepthKnown_A	496457362	496345304	0	0
RvalidKnown_A	496457362	496345304	0	0
WreadyKnown_A	496457362	496345304	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	88092	0	0
T1	440458	77	0	0
T2	61615	13	0	0
T3	193036	30	0	0
T34	387201	60	0	0
T38	130956	94	0	0
T43	685494	26	0	0
T54	120738	53	0	0
T67	70936	8	0	0
T87	83489	13	0	0
T88	80931	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496457362	49751	0	0
DepthKnown_A	496457362	496345304	0	0
RvalidKnown_A	496457362	496345304	0	0
WreadyKnown_A	496457362	496345304	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	49751	0	0
T1	440458	74	0	0
T2	61615	12	0	0
T3	193036	28	0	0
T34	387201	57	0	0
T38	130956	93	0	0
T43	685494	5	0	0
T54	120738	52	0	0
T67	70936	8	0	0
T87	83489	12	0	0
T88	80931	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496457362	49751	0	0
DepthKnown_A	496457362	496345304	0	0
RvalidKnown_A	496457362	496345304	0	0
WreadyKnown_A	496457362	496345304	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	49751	0	0
T1	440458	74	0	0
T2	61615	12	0	0
T3	193036	28	0	0
T34	387201	57	0	0
T38	130956	93	0	0
T43	685494	5	0	0
T54	120738	52	0	0
T67	70936	8	0	0
T87	83489	12	0	0
T88	80931	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496457362	36066	0	0
DepthKnown_A	496457362	496345304	0	0
RvalidKnown_A	496457362	496345304	0	0
WreadyKnown_A	496457362	496345304	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	36066	0	0
T1	440458	3	0	0
T2	61615	1	0	0
T3	193036	2	0	0
T34	387201	3	0	0
T38	130956	1	0	0
T43	685494	21	0	0
T54	120738	1	0	0
T59	0	3	0	0
T67	70936	0	0	0
T87	83489	1	0	0
T88	80931	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	496457362	38341	0	0
DepthKnown_A	496457362	496345304	0	0
RvalidKnown_A	496457362	496345304	0	0
WreadyKnown_A	496457362	496345304	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	38341	0	0
T1	440458	3	0	0
T2	61615	1	0	0
T3	193036	2	0	0
T34	387201	3	0	0
T38	130956	1	0	0
T43	685494	21	0	0
T54	120738	1	0	0
T59	0	3	0	0
T67	70936	0	0	0
T87	83489	1	0	0
T88	80931	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496457362	496345304	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0